Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DMA CONTROLLER
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until the DMA_DONE interrupt is received does not guarantee
expected behavior. It is recommended that the user not update the
descriptor before receiving DMA_DONE.
Example Code: Define DMA Structures
To define DMA structures, use the following code:
memset(dmaChanDesc,0x0,sizeof(dmaChan►
Desc)); // Set up the
DMA base address pointer register.
uiBasPtr = (unsigned int)&dmaChan►
Desc; // Set up the DMA base pointer.
pADI_DMA->CFG = 1; //
Enable DMA controller
pADI_DMA->PDBPTR = uiBasPtr;
SOURCE DATA END POINTER
The SRC_END_PTR memory location stores the address of the
last location from which data is read as part of a DMA transfer. This
memory location must be programmed with the end address of the
source data before the controller can perform a DMA transfer. The
controller reads this memory location when it starts the first DMA
data transfer. The DMA controller does not write to this memory
location.
Table 191. Source Data End Pointer
Bits Name Description
[31:0] SRC_END_PTR The end address of the source data
DESTINATION DATA END POINTER
The DST_END_PTR memory location stores the address of the
last location to which data is written as part of a DMA transfer.
This memory location must be programmed with the end address
of the destination data before the controller can perform a DMA
transfer. The controller reads this memory location when it starts
the first DMA data transfer. The DMA controller does not write to
this memory location.
Table 192. Destination Data End Pointer
Bits Name Description
[31:0] DST_END_PTR The end address of the source data
CONTROL DATA CONFIGURATION
For each DMA transfer, the CHNL_CFG memory location provides
the control information for the DMA transfer to the controller.
Table 193. CHNL_CFG Control Data Configuration
Bit(s) Name
Source
Data Width Setting Description
[31:30] DST_INC Destination Address Increment. The address increment depends on the source data width.
Byte
00 Source address increment is byte.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the DST_END_PTR memory location.
Half word
00 Reserved.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the DST_END_PTR memory location.
Word
00 Reserved.
01 Reserved.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the DST_END_PTR memory location.
[29:28] Reserved Undefined. Write as zero.
[27:26] SRC_INC Source Address Increment. The address increment depends on the source data width.
Byte
00 Source address increment is byte.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.