Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DMA CONTROLLER
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Table 193. CHNL_CFG Control Data Configuration (Continued)
Bit(s) Name
Source
Data Width Setting Description
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory location.
Half word
00 Reserved.
01 Source address increment is half word.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory location.
Word
00 Reserved.
01 Reserved.
10 Source address increment is word.
11 No increment. Address remains set to the value contained in the SRC_END_PTR memory location.
[25:24] SRC_SIZE Size of the Source Data.
00 Byte.
01 Half word.
10 Word.
11 Reserved.
[23:18] Reserved Undefined. Write as 0.
[17:14] R_POWER DMA Transfers Before Rearbitration. Set these bits to control the number of DMA transfers can occur
before the controller rearbitrates. These bits must be set to 0000 for all DMA transfers involving peripherals.
Operation of the DMA is indeterminate if a value other than 0000 is programmed in this location for DMA
transfers involving peripherals.
0000 1
0001 2
0010 4
0011 8
0100 16
0101 32
0110 64
0111 128
1000 256
1001 512
1010 to
1111
1024
[13:4] N_MINUS_1 Number of Configured Transfers Minus 1 for that Channel. The 10-bit value indicates the number of DMA
transfers (not the total number of bytes) minus one.
0x000 1 DMA transfer.
0x001 2 DMA transfers.
0x002 3 DMA transfers.
…
0x3FF 1024 DMA transfers.
3 Reserved Undefined. Write as 0.
[2:0] CYCLE_CTRL Transfer Types of DMA Cycle.
000 Stop (invalid).
001 Basic.
010 Autorequest.
011 Ping pong.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English