Reference Manual ADuCM356
DMA CONTROLLER
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Table 193. CHNL_CFG Control Data Configuration (Continued)
Bit(s) Name
Source
Data Width Setting Description
100 Memory scatter gather primary.
101 Memory scatter gather alternate.
110 Peripheral scatter gather primary.
111 Peripheral scatter gather alternate.
During the DMA transfer process, if any error occurs during the
data transfer, CHNL_CFG is written back to the system memory,
with the N_MINUS_1 bits updated to reflect the number of transfers
yet to be completed. When a full DMA cycle is complete, the
CYCLE_CTRL bits are made invalid to indicate the completion of
the transfer.
DMA PRIORITY
The priority of a channel is determined by its number and priority
level. Each channel can have two priority levels: default or high.
All channels at the high priority level have higher priority than
channels at the default priority level. At the same priority level, a
channel with a lower channel number has a higher priority. The
DMA channel priority levels can be changed by writing to the
appropriate bit in the PRI_SET register.
DMA TRANSFER TYPES
The DMA controller supports several types of DMA transfers. The
various types are selected by programming the appropriate values
into the CYCLE_CTRL bits (Bits[2:0]) in the CHNL_CFG location of
the control data structure.
Invalid (CHNL_CFG, Bits[2:0] = 000)
CHNL_CFG, Bits[2:0] = 000 means that no DMA transfer is enabled
for the channel. After the controller completes a DMA cycle, it sets
the cycle type to invalid to prevent it from repeating the same DMA
cycle.
Basic (CHNL_CFG, Bits[2:0] = 001)
In basic mode, the controller can be configured to use either the
primary or alternate data structure. The peripheral must present
a request for every data transfer. After the channel is enabled,
when the controller receives a request, it performs the following
operations:
1. The controller performs a transfer. If the number of transfers
remaining is zero, skip to Step 3.
2. The controller arbitrates. If a higher priority channel is request-
ing service, the controller services that channel. If the peripheral
or software signals a request to the controller, the controller
returns to Step 1.
3. At the end of the transfer, the controller generates the corre-
sponding DMA_DONE channel interrupt in the NVIC.
Autorequest (CHNL_CFG, Bits[2:0] = 010)
When the controller operates in autorequest mode, it is only neces-
sary for the controller to receive a single request to enable it to
complete the entire DMA cycle. As such, a large data transfer can
occur without significantly increasing the latency for servicing higher
priority requests or requiring multiple requests from the processor
or peripheral. Autorequest mode is very useful for a memory to
memory copy application.
In autorequest mode, the controller can be configured to use either
the primary or alternate data structure. After the channel is enabled,
when the controller receives a request, it performs the following
operations:
1. The controller performs a minimum (2
CHNL_CFG Bits[17:14]
, N)
transfer for the channel, where N is the number of transfers. If
the number of transfers remaining is zero, skip to Step 3.
2. A request for the channel is automatically generated. The
controller arbitrates. If the channel has the highest priority, the
DMA cycle returns to Step 1.
3. At the end of the transfer, the controller generates an interrupt
for the corresponding DMA channel.
Ping Pong (CHNL_CFG, Bits[2:0] = 011)
In ping pong mode, the controller performs a DMA cycle using one
of the data structures and then performs a DMA cycle using the
other data structure. The controller continues to switch between
using the primary and alternate data structures until it reads a data
structure that is invalid, or the MCU disables the channel.
Ping pong mode is useful for transferring data using different buf-
fers in a memory. In a typical application, the host must configure
both primary and alternate data structures before starting the trans-
fer. As the transfer progresses, the host can subsequently configure
primary or alternate control data structures in the interrupt service
routine when the corresponding transfer ends.
The DMA controller interrupts the MCU using the DMA_DONE
interrupt after the completion of transfers associated with each
control data structure. The individual transfers using either the
primary or alternate control data structure work the same as a basic
DMA transfer.
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