Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
CYCLIC REDUNDANCY CHECK
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The CRC accelerator on the digital die computes the CRC for a
block of memory locations on the digital die only. The exact memory
location can be in the SRAM, flash, or any combination of memory
mapped registers. The CRC accelerator generates a checksum
that can be compared to an expected signature. The final CRC
comparison is the responsibility of the MCU. CRC function is not
supported for the AFE die blocks.
CRC FEATURES
The CRC, used by the ADuCM356 MCU, supports the following
features:
► Generation of a CRC signature for a block of data.
► Programmable polynomial length of up to 32 bits.
► Operates on 32 bits of data at a time.
► MSB first and LSB first CRC implementations.
►
Various data mirroring capabilities.
► Initial seed to be programmed by user.
►
DMA controller (using software DMA) can be used for data
transfer to offload workload from the MCU.
CRC FUNCTIONAL DESCRIPTION
The following sections detail the functionality of the CRC. Control
for address decrementation and incrementation options for comput-
ing the CRC on a block of memory is in the DMA controller,
and details on these options can be found in the DMA Controller
section.
Figure 66. CRC Block Diagram
CRC Architectural Concepts
The CRC accelerator works on 32-bit data words, which are either
fed to the block through the DMA channel dedicated to the CRC ac-
celerator or directly by the MCU. The CRC accelerator guarantees
immediate availability of the CRC output.
CRC Operating Modes
The accelerator calculates CRC on the data stream it receives, 32
bits at a time. The CRC is then written into the block using either
the DMA engine or via the MCU directly.
The CRC works on 32-bit data words. For data words less than 32
bits in size, the MCU must pack the data into 32-bit data units. Data
mirroring on the input data can be performed at bit, byte, or word
level (only for 32-bit data) by setting CTL, Bits[4:2].
When operating, the CRC algorithm runs on the incoming data
stream written to the IPDATA register. For every new word of data
received, the CRC is computed and the result register is updated
with the calculated CRC. The CRC accelerator guarantees the
immediate availability of the CRC result up to the current data in the
result register.
The CRC engine uses the current result for generating the next
result when a new data word is received. The result register can
be programmed with an initial seed. The bit width of the seed value
for an x-bit polynomial must be x. The seed must be justified in the
result register.
Polynomial
The CRC accelerator supports the calculation of the CRC using any
length polynomial. The polynomial must be written to the polynomial
register. For MSB first implementation, omit the highest power
while programming the CRC polynomial register and left justify the
polynomial. For LSB first implementation, right justify the polynomial
and omit the LSB. The result register contains x-bit MSBs as a
checksum for an x-bit CRC polynomial.
The following examples illustrate the CRC polynomial.
16-Bit Polynomial Programming for MSB First
Calculation
Polynomial: CRC-16-CCITT
x
16
+ x
12
+ x
5
+ 1 = (1) 0001 0000 0010 0001 = 0x1021
where the largest exponent (x
16
term) is implied. Therefore, the
polynomial is 0001 0000 0010 0001.
When left justified in the polynomial register, the register format is
detailed in Table 397.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.