Reference Manual ADuCM356
ADC CIRCUIT
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54 to Table 57 detail the registers associated with ADC voltage and
gain calibration.
The current input channels (low-power TIA0, low-power TIA1, and
high-speed TIA) have an extra ADC calibration stage to that de-
tailed in Table 54. The extra stage is determined by the gain error
introduced by each TIA gain resistor. When a current channel is
selected by the ADC, its calibration involves the use of a voltage
measurement port relative to the PGA setting (as detailed in Table
54), and the current selection relates to the TIA channel.
Example functions are provided with the EVAL-ADuCM356QSPZ to
demonstrate how to calibrate the ADC.
Table 54. Voltage Channel Offset and Gain Calibration Registers
PGA Gain Setting Low-Power Mode and High-Power Mode Offset Registers Low-Power Mode and High-Power Mode Gain Registers
1 ADCOFFSETGN1 ADCGAINGN1
1.5 ADCOFFSETGN1P5 ADCGAINGN1P5
2 ADCOFFSETGN2 ADCGAINGN2
4 ADCOFFSETGN4 ADCGAINGN4
9 ADCOFFSETGN9 ADCGAINGN9
Table 55. Low-Power TIA0 Channel Offset and Gain Calibration Registers
PGA Gain Setting Offset Registers Gain Registers
1 ADCOFFSETGN1, ADCOFFSETLPTIA0 ADCGAINGN1, ADCGNLPTIA0
1.5 ADCOFFSETGN1P5, ADCOFFSETLPTIA0 ADCGAINGN1P5, ADCGNLPTIA0
2 ADCOFFSETGN2, ADCOFFSETLPTIA0 ADCGAINGN2, ADCGNLPTIA0
4 ADCOFFSETGN4, ADCOFFSETLPTIA0 ADCGAINGN4, ADCGNLPTIA0
9 ADCOFFSETGN9, ADCOFFSETLPTIA0 ADCGAINGN9, ADCGNLPTIA0
Table 56. Low-Power TIA1 Channel Offset and Gain Calibration Registers, Low-Power Mode Only
PGA Gain Setting Offset Registers Gain Registers
1 ADCOFFSETGN1, ADCOFFSETLPTIA1 ADCGAINGN1, ADCGNLPTIA1
1.5 ADCOFFSETGN1P5, ADCOFFSETLPTIA1 ADCGAINGN1P5, ADCGNLPTIA1
2 ADCOFFSETGN2, ADCOFFSETLPTIA1 ADCGAINGN2, ADCGNLPTIA1
4 ADCOFFSETGN4, ADCOFFSETLPTIA1 ADCGAINGN4, ADCGNLPTIA1
9 ADCOFFSETGN9, ADCOFFSETLPTIA1 ADCGAINGN9, ADCGNLPTIA1
Table 57. High-Speed TIA Channel Offset and Gain Calibration Registers
PGA Gain Setting Offset Registers Gain Registers
1 ADCOFFSETGN1, ADCOFFSETHSTIA ADCGAINGN1, ADCGNHSTIA
1.5 ADCOFFSETGN1P5, ADCOFFSETHSTIA ADCGAINGN1P5, ADCGNHSTIA
2 ADCOFFSETGN2, ADCOFFSETHSTIA ADCGAINGN2, ADCGNHSTIA
4 ADCOFFSETGN4, ADCOFFSETHSTIA ADCGAINGN4, ADCGNHSTIA
9 ADCOFFSETGN9, ADCOFFSETHSTIA ADCGAINGN9, ADCGNHSTIA
When calibrating the gain error for the ADC voltage channels
during Analog Devices production testing, the value loaded to the
ADCGAINGN1P5 calibration register is ≥0x4000. To ensure this
value, the target ADC result is higher than normal. The factory trim
value for the ADC reference is 1.82 V, but for calibration purposes,
the target voltage is 1.835 V.
When calculating a real voltage from an ADC conversion on a
channel using the factory gain calibration, the K factor of 1.835 or
1.82 must be taken into account, as shown in Equation 1. If user
ADC gain calibration targets a reference voltage of 1.82 V, then the
K portion of Equation 1 is not required.
ADC DIGITAL SIGNAL PROCESSOR (DSP)
BUILT IN SELF TEST
It is possible to verify the digital logic blocks on the analog die
related to the ADC.
The digital waveform generator can be used to create a digital
pattern that is connected directly to the output filters of the ADC,
bypassing the ADC itself. As a new value is outputted from the
digital waveform generator block to the sinc3 digital filter, the digital
value is shifted through the calibration block and other digital filter
blocks until the digital value reaches the ADC filter result register.
This value can then be fed to the cyclic redundancy check (CRC)
accelerator block on the digital die.
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