Reference Manual ADuCM356
REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS
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Table 359. Bit Descriptions for STA0
Bits Bit Name Settings Description Reset Access
[15:9] Reserved Reserved. 0x0 R
8 RSTCNT Counter Reset Occurring. Indicates that the counter is currently being reset due to an event detection.
CON0, Bit 14 must be set.
0x0 R
7 PDOK Clear Interrupt Register Synchronization. This bit is set automatically when the user sets CLRI0, Bit 0 = 1.
It is cleared automatically when the clear interrupt request has crossed clock domains and taken effect in
the timer clock domain.
0x0 R
1 The interrupt bit is being updated in the timer clock domain.
0 The interrupt is cleared in the timer clock domain.
6 BUSY Timer Busy. This bit informs the user that a write to CON0 is still crossing into the timer clock domain.
Check this bit after writing CON0 and suppress further writes until this bit is cleared.
0x0 R
0 Timer ready to receive commands to control register.
1 Timer not ready to receive commands to control register.
[5:2] Reserved Reserved. 0x0 R
1 CAP Capture Event Pending. A capture of the current timer value has occurred. 0x0 R
0 No capture event is pending.
1 A capture event is pending.
0 TMOUT Timeout Event Occurred. This bit is set automatically when the value of the counter reaches zero while
counting down or reaches full scale when counting up. This bit is cleared when CLRI0, Bit 0 is set by the
user.
0x0 R
0 No timeout event has occurred.
1 A timeout event has occurred.
PWM CONTROL REGISTER
Address: 0x400C0D20, Reset: 0x0000, Name: PWMCON0
Table 360. Bit Descriptions for PWMCON0
Bits Bit Name Settings Description Reset Access
[15:2] Reserved Reserved. 0x0 R
1 IDLE PWM Idle State. This bit is used to set the PWM idle state. 0x0 R/W
0 MATCHEN PWM Match Enabled. This bit is used to control PWM operational mode. 0x0 R/W
0 PWM in toggle mode.
1 PWM in match mode.
PWM MATCH VALUE REGISTER
Address: 0x400C0D24, Reset: 0x0000, Name: PWMMAT0
Table 361. Bit Descriptions for PWMMAT0
Bits Bit Name Settings Description Reset Access
[15:0] MATCHVAL PWM Match Value. The value is used when the PWM is operating in match mode. The PWM output is
asserted when the up or down counter is equal to this match value. PWM output is deasserted again
when a timeout event occurs. If the match value is never reached, or occurs simultaneous to a timeout
event, the PWM output remains idle.
0x0 R/W
INTERRUPT ENABLE REGISTER
Address: 0x400C0D28, Reset: 0x0000, Name: INTEN
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