Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS
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EXTERNAL WAKE-UP INTERRUPT STATUS REGISTER
Address: 0x4004C084, Reset: 0x00000000, Name: XINT_EXT_STAT
Table 47. Bit Descriptions for XINT_EXT_STAT
Bits Bit Name Settings Description Reset Access
[31:6] Reserved Reserved. 0x0 R
5 STAT_UART_RXWKUP Interrupt Status Bit for P0.11/UART_SIN Wake-Up Interrupt. Read only register bit. Cleared
by writing 1 to XINT_CLR, Bit 5.
0x0 R
0 P0.11/UART_SIN wakeup did not generate the interrupt.
1 P0.11/UART_SIN wakeup generated the interrupt.
4 RESERVED Reserved. 0x0 R
3 STAT_EXTINT3 Interrupt Status Bit for External Interrupt 3. This bit is valid if there is an INTC interrupt from
the AFE die to the digital die.
0x0 R
0 External Interrupt 3 did not generate the interrupt.
1 External Interrupt 3 generated the interrupt.
2 RESERVED Reserved. 0x0 R
1 STAT_EXTINT1 Interrupt Status Bit for External Interrupt 1. This bit is valid if there is an interrupt asserted on
SYS_WAKE. Cleared by writing 1 to XINT_CLR, Bit 1. Read only register bit.
0x0 R
0 External Interrupt 1 did not generate the interrupt.
1 External Interrupt 1 generated the interrupt.
0 Reserved Reserved. 0x0 R
EXTERNAL INTERRUPT CLEAR REGISTER
Address: 0x4004C090, Reset: 0x00000000, Name: XINT_CLR
Table 48. Bit Descriptions for XINT_CLR
Bits Bit Name Settings Description Reset Access
[31:6] Reserved Reserved. 0x0 R
5 UART_RX_CLR External Interrupt Clear for P0.11/UART_SIN Wake-Up Interrupt. Set to 1 to clear the interrupt status
flag. Cleared automatically by hardware.
0x0 R/W
4 IRQ3 External Interrupt 3. Set to 1 to clear the interrupt status flag. Cleared automatically by hardware. 0x0 R/W
[3:2] Reserved Reserved. 0x0 R/W
1 IRQ1 External Interrupt 1. Set to 1 to clear the interrupt status flag. Cleared automatically by hardware. 0x0 R/W
0 Reserved Reserved. 0x0 R
NONMASKABLE INTERRUPT CLEAR REGISTER
Address: 0x4004C094, Reset: 0x00000000, Name: XINT_NMICLR
Table 49. Bit Descriptions for XINT_NMICLR
Bits Bit Name Settings Description Reset Access
[31:1] Reserved Reserved. 0x0 R
0 CLR NMI Clear. Set to 1 to clear an interrupt status flag when the NMI interrupt is set. Cleared automatically by
hardware.
0x0 R/W
ANALOG DIE INTERRUPT ENABLE REGISTER
Address: 0x400C0A28, Reset: 0x0000, Name: EI2CON

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English