Reference Manual ADuCM356
ANALOG DIE CIRCUITRY SUMMARY
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The ADuCM356 analog die includes the following eight main
blocks:
â–º
ADC. The ADC is a high-speed SAR ADC with a wide range of
voltage and current input channels. See the ADC Circuit section.
â–º Low-power potentiostat and TIA. This block also includes the
low-power DACs used to set the DC bias voltage of an external
electrochemical sensor. See the Low-Power Potentiostat Amplifi-
ers and Low-Power TIAs section.
â–º High-speed TIA. The high-speed TIA is intended for measuring
AC current signals with the ADC, especially during impedance
measurements. The high-speed TIA supports a wider input sig-
nal bandwidth than the low-power TIA. The current consumption
of the high-speed TIA is higher than that of the low-power TIA.
See the High-Speed TIA Circuits section.
â–º High-speed DAC circuits. The high-speed DAC is designed to
support AC impedance measurements with its specially designed
output excitation amplifier. The AC signal from the output of the
high-speed DAC can be coupled on the DC sensor bias voltage
set by the low-power DAC via the excitation amplifier. See the
High-Speed DAC Circuits section.
â–º Programmable switches connecting external sensor to the high-
speed DAC and the high-speed TIA. The ADuCM356 provides
flexibility in connecting external pins to the high-speed TIA and
excitation amplifier terminals. See the Programmable Switches
Connecting the External Sensor to the High-Speed DAC and
High-Speed TIA section.
â–º Analog die digital circuits. This block includes optional program-
mable timers. See the Analog Die General-Purpose Timers sec-
tion.
â–º Use case configurations. The Use Case Configurations section
describes typical electrochemical sensor use cases and the
configuration of the ADuCM356 for each use case.
â–º Sequencer (see the Sequencer section).
ADC, HIGH-SPEED DAC, AND
ASSOCIATED AMPLIFIERS OPERATING MODE
CONFIGURATION
The ADC and high-speed DAC circuits are flexible in trading current
consumption vs. signal bandwidth. If the ADC and high-speed
DACs are used to measure and generate signals <80 kHz for
low frequency impedance measurements, these blocks can be
configured for low-power mode by clearing PMBW, Bit 0 = 0. This
configuration minimizes power consumption. If the ADC and or
high-speed DAC are used to measure and generate signals >80
kHz for high frequency impedance measurements, set PMBW, Bit 0
= 1.
SYSTEM BANDWIDTH CONFIGURATION
The user must configure the bandwidth setting for the reconstruc-
tion filter of the high-speed DAC, the antialias filter of the ADC,
and the bandwidth of the high-speed TIA, in addition to configuring
PMBW Bit 0. PMBW, Bits[3:2] allow the user to set this configura-
tion. For the HSTIACON register, ensure that HSTIACON, Bits[5:1]
= 00000 in low-power mode and HSTIACON, Bits[5:1] = 11111 in
high-power mode. See Table 20 for more details on the PMBW
register.
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