Reference Manual ADuCM356
REGISTER DETAILS: LOW POWER TIA/POTENTIOSTAT AND DAC CIRCUITS
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Table 114. Bit Descriptions for LPDACSW0 (Continued)
Bits Bit Name Settings Description Reset Access
0 Disconnect direct connection of VBIAS0 DAC output to positive input of low-power Amplifier 0.
Default.
1 Connect VBIAS0 DAC output directly to positive input of low-power Amplifier 0.
3 SW3 LPDAC0 SW3 Control. 0x0 R/W
0 Disconnect VBIAS0 DAC output from low-pass filter and VBIAS0 pin.
1 Connect VBIAS0 DAC output to the low-pass filter and VBIAS0 pin. Default.
2 SW2 LPDAC0 SW2 Control. R/W
0 Disconnect direct connection of VZERO0 DAC output to low-power TIA0 positive input. Default. 0x0
1 Connect VZERO0 DAC output directly to low-power TIA0 positive input.
1 SW1 LPDAC0 SW1 Control. 0x0 R/W
0 Disconnect VZERO0 DAC output from the low-pass filter and VZERO0 pin.
1 Connect VZERO0 DAC output to the low-pass filter and VZERO0 pin. Default.
0 SW0 LPDAC0 SW0 Control. 0x0 R/W
0 Disconnect VZERO0 DAC output from high-speed TIA positive input. Default.
1 Connect VZERO0 DAC output to the high-speed TIA positive input.
LPDAC0 CONTROL REGISTER
Address: 0x400C2128, Reset: 0x00000002, Name: LPDACCON0
Table 115. Bit Descriptions for LPDACCON0
Bits Bit Name Settings Description Reset Access
[31:7] Reserved Reserved. 0x0 R
6 WAVETYPE Low-Power DAC Source. 0x0 R/W
0 Direct from the LPDACDAT0 register.
1 Waveform generator.
5 DACMDE LPDAC0 Switch Settings. Control bit for LPDAC0 output switches. 0x0 R/W
0 LPDAC0 switches set for normal mode. Clear to 0 for normal output switch operation. Default.
1 LPDAC0 switches set for diagnostic mode.
4 VZEROMUX VZERO0 Mux Select. Select which DAC0 output connects to the VZERO0 node. Ensure that the same
value is written to LPDACCON0, Bit 3 = 1. If this bit is cleared to 0, VBIASMUX must be cleared to 0.
0x0 R/W
0 VZERO0 6-bit. Default. Clear to 0 for VZERO0 output to be 6-bit.
1 VZERO0 12-bit. Set to 1 for VZERO0 output to be 12-bit.
3 VBIASMUX VBIAS Mux Select. Select which DAC0 output connects to the VBIAS0 node. Ensure that the same
value is written to LPDACCON, Bit 4. If this bit is set to 1, the VZEROMUX bit must be set to 1. If this bit
is cleared to 0, VZEROMUX bit must be cleared to 0.
0x0 R/W
0 VBIAS0 12-bit. Default. 12-bit DAC connect to VBIAS0.
1 VBIAS0 6-bit. 6-bit DAC connect to VBIAS0.
2 REFSEL LPDAC0 Reference Select. 0x0 R/W
0 VREF_2.5V Reference 0. Selects the low-power 2.5 V reference as the LPDAC0 reference source.
Default.
1 AVDD Reference 1. Set to 1 to select AVDD as the low-power DAC0 reference.
1 PWDEN LPDAC0 Power-Down. Power-down control bit for low-power DAC. 0x1 R/W
0 LPDAC0 powered on. Power on LPDAC0.
1 LPDAC0 powered off. Default. Power down LPDAC0 to open all switches on LPDAC0 output.
0 RSTEN Enable Writes to LPDAC0. Enables writes to LPDACDAT0 register. 0x0 R/W
0 Disable LPDAC0 writes. Default. If cleared to 0, LPDACDAT0 is always 0. Writes to LPDACDAT0 are
disabled.
1 Enable LPDAC0 writes. Set to 1 to enable writes to the LPDACDAT0 register.
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