Reference Manual ADuCM356
REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER
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Table 382. Bit Descriptions for SR1 (Continued)
Bits Bit Name Settings Description Reset Access
1 A previously posted write to CR0 is still awaiting execution. No new posting to this MMR can be
accepted.
[6:0] Reserved Reserved. 0x78 R
COUNT 0 REGISTER
Address: 0x4000140C, Reset: 0x0000, Name: CNT0
CNT0 contains the lower 16 bits of the WUT counter, which maintains a real-time count in elapsed prescaled WUT time units. The
instantaneous value of CNT0 can be read back by the CPU. The CPU can also redefine the value in this register. In this case, the WUT
continues its real-time count from the redefined value.
Any write to CNT0 pends until a corresponding write to CNT1 is carried out by the CPU, so that the combined 32-bit count redefinition can be
executed as a single transaction. CNT0 and CNT1 can be written in any order, but paired twin writes must be carried out by the CPU to have
any effect on the WUT count. A paired write to CNT0 and CNT1 in any order zeroes the prescaler in the WUT and thus causes a redefinition of
elapsed time by the CPU to align exactly with newly created modulo 1 and modulo 60 boundaries. Such a redefinition also causes the WUT to
create a trim boundary and initiate a new trim interval. When the WUT count is redefined by the CPU, no coincident trim adjustment of the count
is carried out.
The WUT supports immediate redefinition of CNT0 and CNT1 while CR0, Bit 0 is active. Alternatively, the CPU can disable the WUT by first
making CR0, Bit 0 inactive while redefining these registers.
Table 383. Bit Descriptions for CNT0
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Lower 16 Prescaled Nonfractional Bits of the WUT Real-Time Count. 0x0 R/W
COUNT 1 REGISTER
Address: 0x40001410, Reset: 0x0000, Name: CNT1
CNT1 contains the upper 16 bits of the WUT counter, which maintains a real-time count in elapsed prescaled WUT time units. Any write to
CNT1 pends until a corresponding write to CNT0 is carried out by the CPU, so that the combined 32-bit count redefinition can be executed as a
single transaction.
Table 384. Bit Descriptions for CNT1
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Upper 16 Prescaled Nonfractional Bits of the WUT Real-Time Count. 0x0 R/W
ALARM 0 REGISTER
Address: 0x40001414, Reset: 0xFFFF, Name: ALM0
ALM0 contains the lower 16 bits of the prescaled nonfractional WUT alarm target time value, where the overall alarm is defined as ALM1,
ALM0, and ALM2.
Any write to ALM0 pends until corresponding writes to ALM1 and ALM2 are carried out by the CPU, so that the combined 47-bit alarm
redefinition can be executed as a single transaction. ALM0, ALM1, and ALM2 can be written in any order, but coordinated, triple writes must
be carried out by the CPU to have any effect on the WUT alarm. ALM0 can be written to regardless of whether the ALMEN or CNTEN bits are
active in the CR0 register.
Table 385. Bit Descriptions for ALM0
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Lower 16 Prescaled Nonfractional Bits of the WUT Alarm Target Time. The alarm register has a different
reset value to the WUT count to avoid spurious alarms.
0xFFFF R/W
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