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ADuCM356
Analog Devices ADuCM356
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Reference Manual
ADuCM356
REGISTER SUMMAR
Y
: ANALOG DIE CIRCUITR
Y
analog.com
Rev
. A | 50 of 312
T
able 51. Analog Die Circuitry Register Summary
Address
Name
Description
Reset
Access
0x400C2000
AFECON
Analog configuration
0x00080000
R/W
49
51
Table of Contents
Main Page
Preface
1
Scope
1
Table of Contents
2
Using the Aducm356 Hardware Reference Manual
9
Number Notations
9
Register Access Conventions
9
Aducm356 Overview
10
Main Features of the Aducm356
10
Clocking Architecture
12
Clocking Architecture Operation
12
Required Clock Ratio between Digital die and Analog die System Clocks
12
Digital die Clock Features
12
Analog die Clock Features
12
Clock Gating
13
Connecting AFE die Clock to Digital die Clock Input
13
Register Summary: Clock Architecture
15
Register Details: Clock Architecture
16
Key Protection for CTL Register
16
Oscillator Control Register
16
Clock Control 0 Register
16
Clock Dividers Register
17
User Clock Gating Control Register
17
Clocking Status Register
18
Clock Divider Configuration Register
18
Clock Gate Enable Register
19
Clock Select Register
19
GPIO Clock Mux Select to GPIO1 Pin Register
20
Key Protection for CLKCON0 Register
20
Clock Control of Low-Power TIA Chop, Watchdog, and Wake-Up Timers Register
20
Key Protection for OSCCON Register
21
Oscillator Control Register
21
High-Power Oscillator Configuration Register
22
Power Mode Configuration Register
22
Power Management Unit
23
Power Management Unit Features
23
Power Management Unit Operation
23
Code Examples
24
Monitor Voltage Control
25
Register Summary: Power Management Unit
27
Register Details: Power Management Unit
28
Power Supply Monitor Interrupt Enable Register
28
Power Supply Monitor Status Register
28
Power Mode Register
29
Key Protection for PWRMOD and SRAMRET Register
29
Control for Retention SRAM During Hibernate Mode Register
29
High-Power Buck Control Register
30
Control for SRAM Parity and Instruction SRAM Register
30
Initialization Status Register
31
Power Modes Register
32
Key Protection for PWRMOD Register
32
Arm Cortex-M3 Processor
33
Arm Cortex-M3 Processor Features
33
Arm Cortex-M3 Processor Operation
33
Arm Cortex-M3 Processor Related Documents
34
System Resets
35
Digital die Reset Operation
35
Register Summary: System Resets
36
Register Details: System Resets
37
Digital die Reset Status Register
37
Always on Reset Status Register
37
Analog die Status Register
37
Programming, Protection, and Debug
38
Booting
38
Security Features
38
Safety Features
38
System Exceptions and Peripheral Interrupts
39
Cortex-M3 and Fault Management
39
Interrupt Sources from the Analog die
41
Clearing Analog die Interrupt Sources
42
Cortex-M3 NVIC Register List
42
External Interrupt Configuration
43
Register Summary: System Exceptions and Peripheral Interrupts
44
Register Details: System Exceptions and Peripheral Interrupts
45
External Interrupt Configuration 0 Register
45
External Wake-Up Interrupt Status Register
46
External Interrupt Clear Register
46
Nonmaskable Interrupt Clear Register
46
Analog die Interrupt Enable Register
46
Analog die Circuitry Summary
48
ADC, High-Speed DAC, and Associated Amplifiers Operating Mode Configuration
48
System Bandwidth Configuration
48
Register Summary: Analog die Circuitry
50
Register Details: Analog die Circuitry
51
AFE Configuration Register
51
ADC Circuit
53
ADC Circuit Overview
53
ADC Circuit Features
53
ADC Circuit Operation
54
ADC Transfer Function
54
ADC Low-Power Current Input Channels
55
ADC Input Circuit
55
ADC Postprocessing Filter Options
55
Averaging, Statistics, and Outlier Detection Options
57
Internal Temperature Sensor Channels
57
ADC Initialization
58
ADC Calibration
58
ADC Digital Signal Processor (DSP) Built in Self Test
59
Voltage Reference Options
60
Register Summary: ADC Circuit
61
Register Details: ADC Circuit
63
ADC Configuration Register
63
ADC Output Filters Configuration Register
64
Raw Result Register
65
DFT Result, Real Part Register
66
DFT Result, Imaginary Part Register
66
Sinc2 and Supply Rejection Filter Result Register
66
Temperature Sensor 0 Result Register
66
Analog Capture Interrupt Enable Register
66
Analog Capture Interrupt Register
67
AFE DSP Configuration Register
68
Temperature Sensor 0 Configuration Register
69
High-Power and Low-Power Buffer Control Register
69
Number of Repeat ADC Conversions Register
70
Buffer Configuration Register
70
Calibration Lock Register
71
Offset Calibration Low-Power TIA0 Channel Register
71
Gain Calibration for Low-Power TIA0 Channel Register
71
Offset Calibration Low-Power TIA1 Channel Register
72
Gain Calibration for Low-Power TIA1 Channel Register
72
Offset Calibration High-Speed TIA Channel Register
72
Gain Calibration for High-Speed TIA Channel Register
73
Offset Calibration Voltage Channel (PGA Gain = 1) Register
73
Gain Calibration Voltage Input Channel (PGA Gain = 1) Register
73
Offset Calibration Voltage Channel (PGA Gain = 1.5) Register
73
Gain Calibration Voltage Input Channel (PGA Gain = 1.5) Register
74
Offset Calibration Voltage Input Channel (PGA Gain = 2) Register
74
Gain Calibration Voltage Input Channel (PGA Gain = 2) Register
74
Offset Calibration Voltage Input Channel (PGA Gain = 4) Register
75
Gain Calibration Voltage Input Channel (PGA Gain = 4) Register
76
Offset Calibration Voltage Input Channel (PGA Gain = 9) Register
76
Gain Calibration Voltage Input Channel (PGA Gain = 9) Register
76
Offset Calibration Temperature Sensor Channel 0 Register
76
Gain Calibration Temperature Sensor Channel 0 Register
77
Minimum Value Check Register
77
Minimum Slow Moving Value Register
77
Maximum Value Check Register
77
Maximum Slow Moving Register
78
Delta Check Register
78
Statistics Module Configuration Register
78
Mean Output Register
78
Key Access for DSPUPDATEEN Register
80
Digital Logic Test Enable Register
80
Temperature Sensor 1 Control Register
80
Low-Power Potentiostat Amplifiers and Low-Power Tias
81
Low-Power Potentiostat Amplifiers
81
Low-Power Tias
81
Low-Power Dacs
84
Register Summary: Low-Power Tia/Potentiostat and Dac Circuits
88
Register Details: Low Power Tia/Potentiostat and DAC Circuits
89
Low-Power TIA Control Bits Channel 0 Register
89
Low-Power TIA Switch Configuration for Channel 0 Register
90
Low-Power TIA Control Bits Channel 1 Register
91
Low-Power TIA Switch Configuration for Channel 1 Register
93
LPDAC0 Data out Register
94
LPDAC0 Switch Control Register
94
LPDAC0 Control Register
95
LPDAC1 Data out Register
96
LPDAC1 Switch Control Register
96
LPDAC1 Control Register
96
Low-Power Reference Control Register
97
High-Speed TIA Circuits
98
Key Features
98
Using DE0 and DE1 Inputs with the High-Speed TIA
99
External RTIA Selection
100
Register Summary: High-Speed TIA Circuits
101
Register Details: High-Speed TIA Circuits
102
High-Speed RTIA Configuration Register
102
DE1 High-Speed TIA Resistor Configuration Register
102
DE0 High-Speed TIA Resistor Configuration Register
102
High-Speed TIA Amplifier Configuration Register
103
High-Speed DAC Circuits
104
High-Speed DAC Output Signal Generation
104
High-Speed DAC Core Power Modes
104
Recommended Configuration in Hibernate Mode
105
High-Speed DAC Filter Options
105
High-Speed DAC Output Attenuation Options
105
Coupling an AC Signal from High-Speed DAC Onto the DC Level Set by Low-Power DAC
106
Avoiding Incoherency Errors between Excitation and Measurement Frequencies During Impedance Measurements
106
Calibrating the High-Speed DAC
106
Register Summary: High-Speed DAC Circuits
108
Register Details: High-Speed DAC Circuits
109
High-Speed DAC Configuration Register
109
Direct Write to DAC Output Control Value Register
109
DAC DC Buffer Configuration Register
109
DAC Gain Register
109
DAC Offset with Attenuator Enabled (Low-Power Mode) Register
110
DAC Offset with Attenuator Disabled (Low-Power Mode) Register
110
DAC Offset with Attenuator Enabled (High-Power Mode) Register
110
DAC Offset with Attenuator Disabled (High-Power Mode) Register
111
Waveform Generator Configuration Register
111
Waveform Generator for Sinusoid Frequency Control Word Register
111
Waveform Generator for Sinusoid Phase Offset Register
112
Waveform Generator for Sinusoid Offset Register
112
Waveform Generator for Sinusoid Amplitude Register
112
Programmable Switches Connecting the External Sensor to the High-Speed DAC and High-Speed TIA
113
DX Switches
113
Px Switches
113
Nx Switches
113
Tx Switches
113
Options for Controlling All Switches
113
Register Summary: Programmable Switches
116
Register Details: Programmable Switches
117
Switch Matrix Configuration Register
117
DX Switch Matrix Full Configuration Register
118
Nx Switch Matrix Full Configuration Register
119
Px Switch Matrix Full Configuration Register
120
Tx Switch Matrix Full Configuration Register
121
DX Switch Matrix Status Register
122
Px Switch Matrix Status Register
123
Nx Switch Matrix Status Register
124
Tx Switch Matrix Status Register
125
Sequencer
127
Sequencer Features
127
Sequencer Overview
127
Sequencer Commands
127
Sequencer Operation
128
Sequencer and FIFO Registers
130
AFE Interrupts
136
Interrupt Controller Interrupts
136
Configuring the Interrupts
136
Custom Interrupts
136
Interrupt Registers
137
Sleep and Wake-Up Timer
143
Sleep and Wake-Up Timer Features
143
Sleep and Wake-Up Timer Overview
143
Configuring a Defined Sequence Order
143
Recommended Sleep and Wake-Up Timer Operation
143
Sleep and Wake-Up Timer Registers
144
Use Case Configurations
148
Hibernate Mode While Maintaining a DC Bias to the Sensor
148
Measuring a DC Current Output
149
Pulse Test (Chronoamperometry)
151
Cyclic Voltammetry
152
AC Impedance Measurement While Maintaining DC Bias to the Sensor
154
DMA Controller
160
DMA Features
160
DMA Overview
160
DMA Analog die
160
DMA Architectural Concepts
160
DMA Operating Modes
161
Channel Control Data Structure
161
Source Data End Pointer
162
Destination Data End Pointer
162
Control Data Configuration
162
DMA Priority
164
DMA Transfer Types
164
DMA Interrupts and Exceptions
167
Endian Operation
169
DMA Channel Enable and Disable
169
DMA Initiator Enable
169
Power-Down Considerations
169
Register Summary: DMA
170
Register Details: DMA
171
Status Register
171
Configuration Register
171
Channel Primary Control Data Base Pointer Register
171
Channel Alternate Control Data Base Pointer Register
171
Channel Software Request Register
171
Channel Request Mask Set Register
172
Channel Request Mask Clear Register
172
Channel Enable Set Register
172
Channel Enable Clear Register
173
Channel Primary Alternate Set Register
173
Channel Primary Alternate Clear Register
173
Channel Priority Set Register
173
Channel Priority Clear Register
174
Bus Error Clear Register
174
Per Channel Bus Error Register
174
Per Channel Invalid Descriptor Clear Register
176
Channel Bytes Swap Enable Set Register
176
Channel Bytes Swap Enable Clear Register
176
Channel Source Address Decrement Enable Set Register
176
Channel Source Address Decrement Enable Clear Register
177
Channel Destination Address Decrement Enable Set Register
177
Channel Destination Address Decrement Enable Clear Register
177
FIFO Configuration Register
178
Data FIFO Read Register
178
Flash Controller
179
Flash Controller Features
179
Flash Controller Overview
179
Supported Commands
179
Protection and Integrity Features
179
Flash Controller Operation
179
Flash Memory Structure
180
Flash Access
181
Reading Flash
181
Erasing Flash
182
Writing Flash
182
Keyhole Writes
182
Burst Writes
182
DMA Writes
183
Protection and Integrity
183
Key Register
185
Clock and Timings
187
Flash Operating Modes
187
Register Summary: Flash Cache Controller
189
Register Details: Flash Cache Controller (FLCC)
190
Status Register
190
Interrupt Enable Register
192
Command Register
192
Write Address Register
193
Write Lower Data Register
193
Write Upper Data Register
195
Lower Page Address Register
195
Upper Page Address Register
195
Key Register
195
Write Abort Address Register
196
Write Protection Register
196
Signature Register
196
User Configuration Register
197
IRQ Abort Enable (Lower Bits) Register
197
IRQ Abort Enable (Upper Bits) Register
197
ECC Configuration Register
197
ECC Status (Address) Register
199
Analog Devices Flash Security Register
199
Sram
200
SRAM Features
200
Instruction Vs. Data SRAM
200
SRAM Retention in Hibernate Mode
201
SRAM Initialization
201
Cache
202
Initialization in Cache and Instruction SRAM
202
Programming Guidelines
202
Register Summary: Cache (FLCC)
203
Register Details: Cache (FLCC)
204
Cache Status Register
204
Cache Setup Register
204
Cache Key Register
204
Silicon Identification
205
Register Summary: System (Digital Die)
206
Register Details: System (Digital Die)
207
Analog Devices Identification (Digital Die) Register
207
Chip Identifier (Digital Die) Register
207
Serial Wire Debug Enable Register
207
Analog Devices Identification (Analog Die) Register
207
Chip Identification (Analog Die) Register
207
16-Bit Scratch Register to Test Interdie Communications Register
208
Digital Inputs and Outputs
209
Digital Inputs and Outputs Features
209
Digital Inputs and Outputs Overview
209
Digital Inputs and Outputs Operation
209
Interrupts
210
Digital die Port Mux
211
AFE die Digital Port Mux
211
Register Summary: Digital Inputs and Outputs
212
Register Details: Digital Inputs and Outputs
214
GPIO Port Configuration Registers
214
GPIO Port Output Enable Registers
214
GPIO Port Input/Output Pull-Up Enable Registers
214
GPIO Port Input Path Enable Registers
215
GPIO Port Registered Data Input Registers
215
GPIO Port Data Output Registers
215
GPIO Port Data Output Set Registers
215
GPIO Port Data Output Clear Registers
217
GPIO Port Pin Toggle Registers
217
GPIO Port Interrupt Polarity Registers
217
GPIO Port Interrupt a Enable Registers
217
GPIO Port Interrupt B Enable Registers
218
GPIO Port Interrupt Status Registers
218
GPIO Port Drive Strength Select Registers
218
AFE GPIO Port Configuration Register
218
AFE GPIO Port Output Enable Register
219
AFE GPIO Port Output Pull-Up and Pull-Down Enable Register
219
AFE GPIO Port Input Path Enable Register
219
AFE GPIO Port Registered Data Input
219
AFE GPIO Port Data Output Register
219
AFE GPIO Port Data Output Set Register
220
AFE GPIO Port Data Output Clear Register
220
AFE GPIO Port Pin Toggle Register
220
I 2 C Serial Interface
221
I 2 C Features
221
I 2 C Overview
221
I 2 C Operation
221
I 2 C Operating Modes
223
Register Summary: I 2 C
226
Register Details: I 2 C
227
Initiator Control Register
227
Initiator Status Register
227
Initiator Receive Data Register
228
Initiator Transmit Data Register
228
Initiator Receive Data Count Register
229
Initiator Current Receive Data Count Register
229
First Initiator Address Byte Register
229
Second Initiator Address Byte Register
229
Serial Clock Period Divisor Register
230
Target Control Register
230
Target I 2 C Status, Error, and IRQ Register
231
Target Receive Register
232
Target Transmit Register
232
Hardware General Call ID Register
232
First Target Address Device ID Register
232
Second Target Address Device ID Register
234
Third Target Address Device ID Register
234
Fourth Target Address Device ID Register
234
Initiator and Target FIFO Status Register
234
Initiator and Target Shared Control Register
235
Automatic Stretch Control for Initiator and Target Mode Register
235
Serial Peripheral Interfaces
237
SPI Features
237
SPI Overview
237
SPI Operation
237
SPI Transfer Initiation
238
SPI Interrupts
240
SPI Wire-Or'ed Mode
240
SPI CSERR Condition
241
Spi Dma
241
SPI and Power-Down Modes
242
Register Summary: SPI0/SPI1
243
Register Details: SPI0/SPI1
244
Status Registers
244
Receive Registers
245
Transmit Registers
245
Baud Rate Selection Registers
245
Configuration Registers
245
Interrupt Configuration Registers
247
Transfer Byte Count Registers
248
DMA Enable Registers
248
FIFO Status Registers
249
Read Control Registers
249
Flow Control Registers
250
Wait Timer for Flow Control Registers
252
Chip Select Override Registers
252
UART Serial Interface
253
UART Overview
253
UART Features
253
UART Operation
253
Register Summary: UART
256
Register Details: UART
257
Transmit Holding Register
257
Receive Buffer Register
257
Interrupt Enable Register
257
Interrupt Identification Register
258
Line Control Register
258
Modem Control Register
259
Line Status Register
259
Modem Status Register
260
Scratch Buffer Register
260
FIFO Control Register
260
Fractional Baud Rate Register
261
Baud Rate Divider Register
261
Second Line Control Register
261
UART Control Register
262
Receive FIFO Count Register
262
Transmit FIFO Count Register
262
RS485 Half-Duplex Control Register
262
Autobaud Control Register
263
Autobaud Status (Low) Register
263
Autobaud Status (High) Register
263
Digital die General-Purpose Timers
264
Digital die General-Purpose Timers Features
264
General-Purpose Timers Overview
264
General-Purpose Timer Operations
264
Register Summary: General-Purpose Timers
267
Register Details: General-Purpose Timers
268
16-Bit Synchronous Load Value Registers
268
16-Bit Timer Synchronous Value Registers
268
Control Registers
268
Clear Interrupt Registers
269
Capture Registers
269
16-Bit Asynchronous Load Value Registers
270
16-Bit Timer Asynchronous Value Registers
270
Status Registers
270
Analog die General-Purpose Timers
272
Analog die General-Purpose Timers Features
272
Afe Pwm
272
Register Summary: Analog die General-Purpose Timers
273
Register Details: Analog die General-Purpose Timers
274
16-Bit Load Value Register
274
16-Bit Timer Value Register
274
Control Register
274
Clear Interrupt Register
275
16-Bit Load Value, Asynchronous Register
275
16-Bit Timer Value, Asynchronous Register
275
Status Register
275
PWM Control Register
276
PWM Match Value Register
276
Interrupt Enable Register
276
16-Bit Load Value Register
277
16-Bit Timer Value Register
277
Control Register
277
Clear Interrupt Register
278
16-Bit Load Value, Asynchronous Register
278
16-Bit Timer Value, Asynchronous Register
278
Status Register
279
PWM Control Register
279
PWM Match Value Register
279
AFE Watchdog Timer
281
Watchdog Timer Features and Block Diagram
281
Watchdog Timer Operation
281
Windowed Watchdog Feature
281
Interrupt Mode
282
Register Summary: AFE Watchdog Timer
283
Register Details: AFE Watchdog Timer
284
Watchdog Timer Load Value Register
284
Current Count Value Register
284
Watchdog Timer Control Register
284
Refresh Watchdog Register
285
Timer Status Register
285
Minimum Load Value Register
286
Digital die Wake-Up Timer
287
Overview
287
Features
287
Regular and Periodic Modulo 60 Interrupts
287
Timer Matching Alarm Value Interrupts
287
WUT Functional Description
287
WUT Operating Modes
288
WUT Recommendations: Clock and Power
288
Register Summary: Digital die Wake-Up Timer
289
Register Details: Digital die Wake-Up Timer
290
Control 0 Register
290
Status 0 Register
291
Status 1 Register
293
Count 0 Register
294
Count 1 Register
294
Alarm 0 Register
294
Alarm 1 Register
295
Gateway Register
295
Control 1 Register
295
Status 2 Register
296
Snapshot 0 Register
298
Snapshot 1 Register
298
Snapshot 2 Register
298
Modulo Register
299
Count 2 Register
299
Alarm 2 Register
301
Status 6 Register
301
Cyclic Redundancy Check
303
CRC Features
303
CRC Functional Description
303
CRC Data Transfer
306
CRC Interrupts and Exceptions
306
CRC Programming Model
306
Register Summary: CRC
308
Register Details: CRC
309
CRC Control Register
309
Input Data Word Register
309
CRC Result Register
309
Programmable CRC Polynomial Register
309
Input Data Bits Register
309
Input Data Byte Register
310
Hardware Design Considerations
311
Typical System Configuration
311
Serial Wire Debug Interface
311
Rev. a | 6 of
312
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