Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: ANALOG DIE GENERAL-PURPOSE TIMERS
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Table 365. Bit Descriptions for CTL (Continued)
Bits Bit Name Settings Description Reset Access
4 EN Timer Enable. Used to enable and disable the timer. Clearing this bit resets the timer, including the
CURCNT register.
0x0 R/W
0 Timer is disabled. Default.
1 Timer is enabled.
3 MODE Timer Mode. This bit is used to control whether the timer runs in periodic or free running mode. In
periodic mode, the up or down counter starts at the defined ALOAD, Bits[15:0]. In free running mode, the
up or down counter starts at 0x0000 or 0xFFFF, depending on whether the timer is counting up or down.
0x1 R/W
1 Timer runs in periodic mode. Default.
0 Timer runs in free running mode.
2 UP Count Up. Used to control whether the timer increments (counts up) or decrements (counts down) the up
or down counter.
0x0 R/W
1 Timer is set to count up.
0 Timer is set to count down. Default.
[1:0] PRE Prescaler. Controls the prescaler division factor applied to the selected clock of the timer. 0x2 R/W
00 Source clock/1 or source clock/4. When CTL, Bit 15 is set, source clock/1. When cleared, source clock/4.
01 Source clock/16.
10 Source clock/64.
11 Source clock/256.
CLEAR INTERRUPT REGISTER
Address: 0x400C0E0C, Reset: 0x0000, Name: CLRINT
Table 366. Bit Descriptions for CLRINT
Bits Bit Name Settings Description Reset Access
[15:2] Reserved Reserved. 0x0 R
1 EVTCAPT Clear Captured Event Interrupt. This bit is used to clear a capture event interrupt. 0x0 W1C
1 Clear the capture event interrupt.
0 No effect.
0 TIMEOUT Clear Timeout Interrupt. This bit is used to clear a timeout interrupt. 0x0 W1C
1 Clears the timeout interrupt.
0 No effect.
16-BIT LOAD VALUE, ASYNCHRONOUS REGISTER
Address: 0x400C0E14, Reset: 0x0000, Name: ALOAD
Only use when a synchronous clock source is selected (CTL, Bits[6:5] = 00).
Table 367. Bit Descriptions for ALOAD
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Load Value, Asynchronous. The up or down counter is periodically loaded with this value if periodic mode
is selected (CTL, Bit 5 = 1). Writing this register takes advantage of having the timer run on PCLK by
bypassing clock synchronization logic that is otherwise required.
0x0 R/W
16-BIT TIMER VALUE, ASYNCHRONOUS REGISTER
Address: 0x400C0E18, Reset: 0x0000, Name: ACURCNT
Only use when a synchronous clock source is selected (CTL, Bits[6:5] = 00).

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.