Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
DIGITAL INPUTS AND OUTPUTS
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Input/Output Pull-Up Enable (GPxPE)
In input mode, the GPxPE registers enable and disable internal
pull-up resistors. All Port 0, Port 1, and Port 2 pins have internal
pull-up resistors. The pull-up resistors are implemented as metal-
oxide semiconductor field effect transistors (MOSFETs), with typical
performance shown in Figure 56.
GPIO Interrupt Enable (GPxIEN)
These registers enable the input pin interrupt sources for individual
GPIO pins.
Bit Toggle Mode
Bit toggle mode toggles one or more GPIO data outputs without
affecting other outputs within a port. Only the GPIO pins corre-
sponding to 1 in the GPxTGL registers are toggled. The remaining
GPIOs are unaffected.
INTERRUPTS
Each GPIO pin can be associated with an interrupt. Interrupts
can be independently enabled for each GPIO pin and are always
edge detecting. Only one interrupt is generated with each GPIO
pin transition. The polarity of the detected edge can be positive
(low to high) or negative (high to low). Each GPIO interrupt event
can be mapped to one of two interrupts, Interrupt A or Interrupt B,
allowing the system more flexibility in terms of how GPIO interrupts
are grouped for servicing and how interrupt priorities are set. The
interrupt status of each GPIO pin can be determined and cleared
by accessing the GPxINT status registers. Set the appropriate bit in
the GPxIEN registers to enable the full input path.
Interrupt Polarity
The polarity of the interrupt determines if the interrupt is accepted
on the rising or the falling edge. Each GPIO pin has a correspond-
ing interrupt register (GPxPOL) based on the port in which it is
grouped. The interrupt registers configure the interrupt polarity of
each pin. When set to 0, an interrupt event latches on a high to
low transition on the corresponding pin. When set to 1, an interrupt
event latches on a low to high transition on the corresponding pin.
Interrupt A Enable
Each GPIO port has a corresponding Interrupt Enable A register
(GPxIENA) that is enabled or masked for each pin in the port. The
bits in these registers determine if a latched edge event interrupts
the core (Interrupt A) or is masked. In either case, the occurrence of
the event is captured in the corresponding bit of the GPxINT status
register. When set to 0, Interrupt A is not enabled (masked). No
interrupts to the core are generated by this GPIO pin. When set
to 1, Interrupt A is enabled. On a valid detected edge, an interrupt
source to the core is generated.
Interrupt B Enable
Each GPIO port has a corresponding Interrupt Enable B (GPxIENB)
register that is enabled or masked for each pin in the port. The bits
in these registers determine if a latched edge event interrupts the
core (Interrupt B) or is masked. In either case, the occurrence of
the event is captured in the corresponding bit of the GPxINT status
register. When set to 0, Interrupt B is not enabled (masked). No
interrupts to the core are generated by this GPIO pin. When set
to 1, Interrupt B is enabled. On a valid detected edge, an interrupt
source to the core is generated.
Interrupt Status
Each GPIO port has an interrupt status register (GPxINT) that
captures the interrupts occurring on its pins. These register bits
indicate that the appropriately configured rising or falling edge has
been detected on the corresponding GPIO pin.
When an event is detected, GPxINT remains set until cleared, even
if the GPIO pin transitions back to a nonactive state. Out of reset,
pull-up resistors combined with falling edge detect can result in the
GPxINT status being cleared. However, this may not be the case
if external circuits change the voltage level on the pin. Check the
status of the GPxINT registers before enabling the GPxIENA and
GPxIENB interrupts initially, as well as any time the GPIOx pins are
configured.
Interrupt bits are cleared by writing 1 to the appropriate bit location
in GPxINT. Writing 0 has no effect. If interrupts are enabled to the
core (GPxIENA, GPxIENB), an interrupt GPxINT value of 1 results
in an interrupt to the core. Clear this GPxINT bit during servicing
of the interrupt. When GPxINT is read as 0, a rising or falling edge
is not detected on the corresponding GPIO pin since this bit was
last cleared. When read as 1, a rising or falling edge (GPxPOL
selectable) is detected on the corresponding GPIO pin. This bit can
be software cleared by writing 1 to the appropriate GPxINT bit.
The following is example code to enable BM/P1.1 as an input
interrupt:
pADI_GPIO1->PE =
0x2; // Enable internal
pull-up resistors on P1.1
pADI_GPIO1->IEN =
0x1; // Enable P1.1 input
path
pADI_GPIO1->IENA = 0x2; //
Enable External Interrupt A on P1.11
pADI_GPIO1->POL =
0x0; // Interrupt on fall►
ing edge
NVIC_EnableIRQ(SYS_GPIO_IN►
TA_IRQn); // Enable GPIO_INTA inter►
rupt source in NVIC

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.