Reference Manual ADuCM356
DIGITAL INPUTS AND OUTPUTS
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Input/Output Pull-Up Enable (GPxPE)
In input mode, the GPxPE registers enable and disable internal
pull-up resistors. All Port 0, Port 1, and Port 2 pins have internal
pull-up resistors. The pull-up resistors are implemented as metal-
oxide semiconductor field effect transistors (MOSFETs), with typical
performance shown in Figure 56.
GPIO Interrupt Enable (GPxIEN)
These registers enable the input pin interrupt sources for individual
GPIO pins.
Bit Toggle Mode
Bit toggle mode toggles one or more GPIO data outputs without
affecting other outputs within a port. Only the GPIO pins corre-
sponding to 1 in the GPxTGL registers are toggled. The remaining
GPIOs are unaffected.
INTERRUPTS
Each GPIO pin can be associated with an interrupt. Interrupts
can be independently enabled for each GPIO pin and are always
edge detecting. Only one interrupt is generated with each GPIO
pin transition. The polarity of the detected edge can be positive
(low to high) or negative (high to low). Each GPIO interrupt event
can be mapped to one of two interrupts, Interrupt A or Interrupt B,
allowing the system more flexibility in terms of how GPIO interrupts
are grouped for servicing and how interrupt priorities are set. The
interrupt status of each GPIO pin can be determined and cleared
by accessing the GPxINT status registers. Set the appropriate bit in
the GPxIEN registers to enable the full input path.
Interrupt Polarity
The polarity of the interrupt determines if the interrupt is accepted
on the rising or the falling edge. Each GPIO pin has a correspond-
ing interrupt register (GPxPOL) based on the port in which it is
grouped. The interrupt registers configure the interrupt polarity of
each pin. When set to 0, an interrupt event latches on a high to
low transition on the corresponding pin. When set to 1, an interrupt
event latches on a low to high transition on the corresponding pin.
Interrupt A Enable
Each GPIO port has a corresponding Interrupt Enable A register
(GPxIENA) that is enabled or masked for each pin in the port. The
bits in these registers determine if a latched edge event interrupts
the core (Interrupt A) or is masked. In either case, the occurrence of
the event is captured in the corresponding bit of the GPxINT status
register. When set to 0, Interrupt A is not enabled (masked). No
interrupts to the core are generated by this GPIO pin. When set
to 1, Interrupt A is enabled. On a valid detected edge, an interrupt
source to the core is generated.
Interrupt B Enable
Each GPIO port has a corresponding Interrupt Enable B (GPxIENB)
register that is enabled or masked for each pin in the port. The bits
in these registers determine if a latched edge event interrupts the
core (Interrupt B) or is masked. In either case, the occurrence of
the event is captured in the corresponding bit of the GPxINT status
register. When set to 0, Interrupt B is not enabled (masked). No
interrupts to the core are generated by this GPIO pin. When set
to 1, Interrupt B is enabled. On a valid detected edge, an interrupt
source to the core is generated.
Interrupt Status
Each GPIO port has an interrupt status register (GPxINT) that
captures the interrupts occurring on its pins. These register bits
indicate that the appropriately configured rising or falling edge has
been detected on the corresponding GPIO pin.
When an event is detected, GPxINT remains set until cleared, even
if the GPIO pin transitions back to a nonactive state. Out of reset,
pull-up resistors combined with falling edge detect can result in the
GPxINT status being cleared. However, this may not be the case
if external circuits change the voltage level on the pin. Check the
status of the GPxINT registers before enabling the GPxIENA and
GPxIENB interrupts initially, as well as any time the GPIOx pins are
configured.
Interrupt bits are cleared by writing 1 to the appropriate bit location
in GPxINT. Writing 0 has no effect. If interrupts are enabled to the
core (GPxIENA, GPxIENB), an interrupt GPxINT value of 1 results
in an interrupt to the core. Clear this GPxINT bit during servicing
of the interrupt. When GPxINT is read as 0, a rising or falling edge
is not detected on the corresponding GPIO pin since this bit was
last cleared. When read as 1, a rising or falling edge (GPxPOL
selectable) is detected on the corresponding GPIO pin. This bit can
be software cleared by writing 1 to the appropriate GPxINT bit.
The following is example code to enable BM/P1.1 as an input
interrupt:
pADI_GPIO1->PE =
0x2; // Enable internal
pull-up resistors on P1.1
pADI_GPIO1->IEN =
0x1; // Enable P1.1 input
path
pADI_GPIO1->IENA = 0x2; //
Enable External Interrupt A on P1.11
pADI_GPIO1->POL =
0x0; // Interrupt on fallâ–º
ing edge
NVIC_EnableIRQ(SYS_GPIO_INâ–º
TA_IRQn); // Enable GPIO_INTA interâ–º
rupt source in NVIC
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