Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
POWER MANAGEMENT UNIT
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The following function configures the digital die operating mode:
int PwrCfg(int iMode,int iMonVbBat,int iSram►
Ret)
{
int32_t index = 0;
uint32_t savedWDT;
savedWDT = pADI_WDT0->CTL; //None of the
watchdog timer registers are retained in hiber►
nate mode
if (iMode > 3) // Check for invalid
sleep mode value
{
iMode = 0;
return 1;
}
if ((iMode == 2) || (iMode == 3))
{
SCB->SCR = 0x04; // sleepdeep mode -
write to the Cortex-m3 System Control register
bit2
}
pADI_PMG0->PWRKEY = 0x4859; // key1
pADI_PMG0->PWRMOD = iMode|iMonVbBat;
for (index=0;index<2;index++);
__WFI();
for (index=0;index<2;index++);
pADI_WDT0->CTL = savedWDT; //restore WDT
control register.
return 1;
}
Wake-Up Sequence
The digital die wake-up mechanism is different for each power-
down mode. The wake-up is triggered by an interrupt or a reset.
The sequence for the wake-up is different depending on the power
mode. If the wake-up is triggered by a coming interrupt, the system
first executes the interrupt routine.
The analog die exits hibernate mode when the digital die tries to
read or write to any analog die register. When the Arm Cortex-M3
executes an instruction to access any analog die register when the
analog die is in hibernate mode, the CPU halts until that instruction
is complete. The CPU must wait for the analog die to complete its
wake-up sequence before resuming.
The user must reset the ALLON PWRMOD register to active mode
after the wake-up sequence is complete. This reset ensures that
the analog die exits hibernate mode correctly when required in the
user application.
This following code example shows how to wake up the analog die
after the digital die has exited hibernate mode:
uiDummyRead = pADI_AFE->LPDACCON0; // read any
analog die register to wake-up analog die
AfePwrCfg(AFE_ACTIVE); // reset
pADI_ALLON->PWRMOD[1:0] = 0b01
The ADC reference requires 110 μs to settle after the analog die
exits hibernate mode. Do not start any ADC conversions until this
period has elapsed.
MONITOR VOLTAGE CONTROL
The user code must monitor the chip power supply voltages. The
AFE die peripherals are not specified to operate at voltages <2.8 V.
The ADuCM356 provides a number of features to help user code
monitor the AVDD and DVDD supply rails of the ADuCM356.
On the digital die, voltage supervisory circuits are enabled at all
times to guarantee that the AVDD_DD supply (2.8 V to 3.6 V) and
the regulated supply are always within operating levels. The circuit
monitoring these supplies is called the PMU.
The main features for the PMU circuit during active mode are as
follows:
► Monitors DVDD voltage. Generates a reset to the chip if
AVDD_DD supply is below 1.6 V. The analog die generates
a reset at a higher voltage. Refer to the specifications section in
the ADuCM356 data sheet for details.
► Monitors the state of the AVDD_DD. Generates AVDD_DD pow-
er supply monitor (PSM) interrupts between 3.6 V and 2.75 V,
and AVDD_DD PSM interrupts between 2.75 V and 2.3 V. These
ranges of interrupts are enabled by the PMG0 IEN register.
► Monitors regulated supply.
► Generates an interrupt if the DVDD_REG regulated supply is
greater than 1.32 V (overvoltage).
► Generates an interrupt if the DVDD_REG regulated supply is
less than 1.1 V (undervoltage).
► Generates a reset if the DVDD_REG regulated supply is
below 1.08 V.
The main features for the PMU during hibernate mode are as
follows:
► Monitors battery voltage.
►
Generates an alarm to the processor if the supply voltage is
less than 1.83 V (optional).
► Generates a reset to the chip if the supply is less than 1.6 V
(optional).
► Monitors the state of the optional battery monitor feature. The
PMU also provides optional battery monitoring between 3.6 V
and 2.75 V, and battery between 2.75 V and 2.3 V.
► Monitors regulated supply. Generates a reset if the DVDD_REG
regulated supply is below 1.08 V.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.