Reference Manual ADuCM356
POWER MANAGEMENT UNIT
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The following function configures the digital die operating mode:
int PwrCfg(int iMode,int iMonVbBat,int iSramâ–º
Ret)
{
int32_t index = 0;
uint32_t savedWDT;
savedWDT = pADI_WDT0->CTL; //None of the
watchdog timer registers are retained in hiberâ–º
nate mode
if (iMode > 3) // Check for invalid
sleep mode value
{
iMode = 0;
return 1;
}
if ((iMode == 2) || (iMode == 3))
{
SCB->SCR = 0x04; // sleepdeep mode -
write to the Cortex-m3 System Control register
bit2
}
pADI_PMG0->PWRKEY = 0x4859; // key1
pADI_PMG0->PWRMOD = iMode|iMonVbBat;
for (index=0;index<2;index++);
__WFI();
for (index=0;index<2;index++);
pADI_WDT0->CTL = savedWDT; //restore WDT
control register.
return 1;
}
Wake-Up Sequence
The digital die wake-up mechanism is different for each power-
down mode. The wake-up is triggered by an interrupt or a reset.
The sequence for the wake-up is different depending on the power
mode. If the wake-up is triggered by a coming interrupt, the system
first executes the interrupt routine.
The analog die exits hibernate mode when the digital die tries to
read or write to any analog die register. When the Arm Cortex-M3
executes an instruction to access any analog die register when the
analog die is in hibernate mode, the CPU halts until that instruction
is complete. The CPU must wait for the analog die to complete its
wake-up sequence before resuming.
The user must reset the ALLON PWRMOD register to active mode
after the wake-up sequence is complete. This reset ensures that
the analog die exits hibernate mode correctly when required in the
user application.
This following code example shows how to wake up the analog die
after the digital die has exited hibernate mode:
uiDummyRead = pADI_AFE->LPDACCON0; // read any
analog die register to wake-up analog die
AfePwrCfg(AFE_ACTIVE); // reset
pADI_ALLON->PWRMOD[1:0] = 0b01
The ADC reference requires 110 μs to settle after the analog die
exits hibernate mode. Do not start any ADC conversions until this
period has elapsed.
MONITOR VOLTAGE CONTROL
The user code must monitor the chip power supply voltages. The
AFE die peripherals are not specified to operate at voltages <2.8 V.
The ADuCM356 provides a number of features to help user code
monitor the AVDD and DVDD supply rails of the ADuCM356.
On the digital die, voltage supervisory circuits are enabled at all
times to guarantee that the AVDD_DD supply (2.8 V to 3.6 V) and
the regulated supply are always within operating levels. The circuit
monitoring these supplies is called the PMU.
The main features for the PMU circuit during active mode are as
follows:
â–º Monitors DVDD voltage. Generates a reset to the chip if
AVDD_DD supply is below 1.6 V. The analog die generates
a reset at a higher voltage. Refer to the specifications section in
the ADuCM356 data sheet for details.
â–º Monitors the state of the AVDD_DD. Generates AVDD_DD pow-
er supply monitor (PSM) interrupts between 3.6 V and 2.75 V,
and AVDD_DD PSM interrupts between 2.75 V and 2.3 V. These
ranges of interrupts are enabled by the PMG0 IEN register.
â–º Monitors regulated supply.
â–º Generates an interrupt if the DVDD_REG regulated supply is
greater than 1.32 V (overvoltage).
â–º Generates an interrupt if the DVDD_REG regulated supply is
less than 1.1 V (undervoltage).
â–º Generates a reset if the DVDD_REG regulated supply is
below 1.08 V.
The main features for the PMU during hibernate mode are as
follows:
â–º Monitors battery voltage.
â–º
Generates an alarm to the processor if the supply voltage is
less than 1.83 V (optional).
â–º Generates a reset to the chip if the supply is less than 1.6 V
(optional).
â–º Monitors the state of the optional battery monitor feature. The
PMU also provides optional battery monitoring between 3.6 V
and 2.75 V, and battery between 2.75 V and 2.3 V.
â–º Monitors regulated supply. Generates a reset if the DVDD_REG
regulated supply is below 1.08 V.
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