Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: SPI0/SPI1
analog.com Rev. A | 248 of 312
Table 311. Bit Descriptions for SPI0_IEN, SPI1_IEN (Continued)
Bits Bit Name Settings Description Reset Access
001 Transmit interrupt occurs when 2 bytes have been transferred. Receive interrupt occurs when 2 or more
bytes have been received into the FIFO.
010 Transmit interrupt occurs when 3 bytes have been transferred. Receive interrupt occurs when 3 or more
bytes have been received into the FIFO.
011 Transmit interrupt occurs when 4 bytes have been transferred. Receive interrupt occurs when 4 or more
bytes have been received into the FIFO.
100 Transmit interrupt occurs when 5 bytes have been transferred. Receive interrupt occurs when 5 or more
bytes have been received into the FIFO.
101 Transmit interrupt occurs when 6 bytes have been transferred. Receive interrupt occurs when 6 or more
bytes have been received into the FIFO.
110 Transmit interrupt occurs when 7 bytes have been transferred. Receive interrupt occurs when 7 or more
bytes have been received into the FIFO.
111 Transmit interrupt occurs when 8 bytes have been transferred. Receive interrupt occurs when the FIFO is
full.
TRANSFER BYTE COUNT REGISTERS
Address: 0x40004018, Reset: 0x0000, Name: SPI0_CNT
Address: 0x40024018, Reset: 0x0000, Name: SPI1_CNT
This register is only used in initiator mode.
Table 312. Bit Descriptions for SPI0_CNT, SPI1_CNT
Bits Bit Name Settings Description Reset Access
15 FRAMECONT Continue Frame. Use this bit in conjunction with the SPIx_CTL, Bit 11 and SPIx_CNT, Bits[13:0] fields.
This bit is used to control SPI data framing.
0x0 R/W
0 When writing to this bit, if this bit is cleared, the SPI initiator transfers only one frame of SPIx_CNT,
Bits[13:0]. When reading this bit, if the value bits > 0, stop SPI transfers after the specified number of
bytes.
1 When writing to this bit, the SPI initiator transfers data in frames of SPIx_CNT, Bits[13:0] bytes per
frame. If SPIx_CNT, Bits[13:0] = 0, this field has no effect because the SPI initiator continues with
transfers as long as the transmit or receive FIFO is ready. If SPIx_CTL, Bit 11 = 0, this field has no
effect because all SPI frames are a single byte wide, irrespective of other control fields. When reading
this bit, continue SPI transfers as long as the transmit or receive FIFO is ready.
14 Reserved Reserved. 0x0 R
[13:0] VALUE Transfer Byte Count. This field specifies the number of bytes to be transferred. It is used in both
receive and transmit transfer types. This value ensures that an initiator mode transfer terminates at the
proper time and that 16-bit SPIx_DMA transfers are byte padded or discarded as required to match
odd transfer counts. Reset by clearing SPIx_CTL, Bit 0 to 0.
0x0 R/W
DMA ENABLE REGISTERS
Address: 0x4000401C, Reset: 0x0000, Name: SPI0_DMA
Address: 0x4002401C, Reset: 0x0000, Name: SPI1_DMA
Table 313. Bit Descriptions for SPI0_DMA, SPI1_DMA
Bits Bit Name Settings Description Reset Access
[15:3] Reserved Reserved. 0x0 R
2 RXEN Enable Receive DMA Request. 0x0 R/W
0 Disable receive DMA interrupt.
1 Enable receive DMA interrupt.
1 TXEN Enable Transmit DMA Request. 0x0 R/W

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.