Reference Manual ADuCM356
SERIAL PERIPHERAL INTERFACES
analog.com Rev. A | 237 of 312
SPI FEATURES
The ADuCM356 integrates two complete hardware SPIs with the
following standard features:
â–º Serial clock phase mode and serial clock polarity mode.
â–º LSB first transfer option.
â–º Loopback mode.
â–º Initiator or target mode.
â–º Flow control, the SPI for Channel 1 (SPI1) channel only.
â–º Support for 3-pin SPI initiator or target, single bidirectional data
pin.
â–º Transfer and interrupt mode.
â–º Continuous transfer mode.
â–º Transmit and receive FIFO.
â–º Interrupt mode. Interrupt after one byte to eight bytes.
â–º Receive overflow mode and transmit under run mode.
â–º Open circuit data output mode.
â–º Full duplex communications supported (simultaneous transmit
and receive).
SPI OVERVIEW
The ADuCM356 integrates two complete hardware SPIs. SPI is an
industry-standard, synchronous serial interface that allows eight bits
of data to be synchronously transmitted and simultaneously re-
ceived (also known as full duplex). The two SPIs implemented on
the ADuCM356 can operate to a maximum bit rate of 6.5 Mbps in
both initiator and target modes.
Optional modes of operation include the following:
â–º Flow control. Supported by SPI1, which has an optional extra
ready pin (P0.3/SPI0_CS). Flow control helps slow target devi-
ces to interface with fast initiators. Another option available is to
insert wait states during ready data, which is helpful in initiator
mode when the user is looking to read bursts of data from a
target and leave a timing gap between each burst. The gap or
wait state is timer controlled.
â–º Fast mode.
â–º 3-pin mode. The SPI0_MOSI and SPI1_MOSI pins in this mode
are bidirectional pins.
The SPI blocks have an additional DMA feature. Each SPI block
has two DMA channels that interface with a microDMA controller
of the Arm Cortex-M3 processor. One DMA channel is used for
transmitting data, and the other is used for receiving data.
SPI OPERATION
In SPI operation, CS refers to the SPI0_CS pin and the SPI1_CS
pin, SCLK refers to the SPI0_CLK pin and the SPI1_CLK pin, MOSI
refers to the SPI0_MOSI pin and the SPI1_MOSI pin, and MISO
refers to the SPI0_MISO pin and the SPI1_MISO pin.
The SPI port can be configured for initiator or target operation,
and consists of four sets of pins: MISO, MOSI, SCLK, and CS.
The GPIOs used for SPI communication must be configured in
SPI mode before enabling the SPI peripheral. Enable the internal
pull-up resistors on the MISO and MOSI pins when communicating
over SPI.
MISO Pin
The MISO pin is configured as an input line in initiator mode and an
output line in target mode. The MISO line on the initiator (data in)
must be connected to the MISO line in the target device (data out).
The data is transferred as byte wide (8-bit) serial data, MSB first.
MOSI Pin
The MOSI pin is configured as an output line in initiator mode and
an input line in target mode. The MOSI line on the initiator (data
out) must be connected to the MOSI line in the target device (data
in). The data is transferred as byte wide (8-bit) serial data, MSB
first.
SCLK Pin
The initiator SCLK synchronizes the data being transmitted and
received through the MOSI SCLK period. Therefore, a byte is trans-
mitted or received after eight SCLK periods. SCLK is configured as
an output in initiator mode and as an input in target mode.
In initiator mode, the SPIx_CTL register controls the polarity and
phase of the clock, and the bit rate is defined in the SPIx_DIV regis-
ter as follows:
f
SCLK
=
PCLK
2 × 1 + SPIx_DIV
5: 0
(27)
where PCLK is the system clock divided by the factor set in CTL1,
Bits[13:8].
By reducing the clock rate to the SPI blocks, it is possible to reduce
the power consumption of the SPI block. The maximum data rate is
13 Mbps.
In target mode, the SPIx_CTL register must be configured with the
phase and polarity of the expected input clock. The target accepts
data from an external initiator up to 20 Mbps. In both initiator and
target mode, data is transmitted on one edge of the SCLK signal
and sampled on the other. Therefore, it is important that the polarity
and phase be configured the same for the initiator and target
devices.
P0.3/SPI0_CS Pin and P1.5/SPI1_CS Pin
In SPI target mode, a transfer is initiated by the assertion of the
chip select, which is an active low input signal. The SPI port then
transmits and receives 8-bit data until the transfer is concluded by
deassertion of CS. In target mode, CS is always an input.
To Next Page
Loading...
Need help?
General