Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: I
2
C
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Table 303. Bit Descriptions for ASTRETCH_SCL (Continued)
Bits Bit Name Settings Description Reset Access
DIV 15: 8 + DIV 7: 4 − 1
UCLK/CTL 1 13:8 − CTL 1 13:8
× 2
ASTRETCH_SCL 7: 4
Note that the I
2
C bus baud rate has no influence on the target stretch timeout period.
1111 Automatic target clock stretching enabled with indefinite timeout period.
[3:0] MST Automatic Stretch Mode Control for Initiator. These bits control automatic stretch mode for initiator
operation. These bits allow the initiator to hold the I2C_SCL line low and gain more time to service
an interrupt, load a FIFO, or read a FIFO. Use the timeout feature to avoid a bus lockup condition
where the initiator indefinitely holds I2C_SCL low. As an initiator transmitter, I2C_SCL is automatically
stretched from the negative edge of I2C_SCL (if the initiator transmit FIFO is empty) before sending an
acknowledge or a no acknowledge for an address byte, or before sending data for a data byte. Stretching
stops when the initiator transmit FIFO is no longer empty or a timeout occurs. As an initiator receiver,
the I2C_SCL clock is automatically stretched from the negative edge of I2C_SCL before sending an
acknowledge or a no acknowledge when the initiator receive FIFO is full. Stretching stops when the
initiator receive FIFO is no longer in an overflow condition or a timeout occurs.
0x0 R/W
0000 Automatic initiator clock stretching disabled.
0001 to 1110 Automatic initiator clock stretching enabled. The timeout period is defined as follows:
DIV 15: 8 + DIV 7: 4 − 1
UCLK/CTL 1 13:8 − CTL 1 13:8
× 2
ASTRETCH_SCL 3: 0
1111 Automatic initiator clock stretching enabled with indefinite timeout period.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English