Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)
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STATUS REGISTER
Address: 0x40018000, Reset: 0x00000000, Name: STAT
This register provides information on current command states, error detection, and correction.
Table 224. Bit Descriptions for STAT
Bits Bit Name Settings Description Reset Access
[31:30] Reserved Reserved. 0x0 R
29 CACHESRAMPERR SRAM Parity Errors in Cache Controller. This register provides details for AHB errors
generated due to cache SRAM parity error on the ICode bus.
0x0 R
[28:27] ECCDCODE DCode AHB Error ECC Status. Provides details for AHB errors generated due to ECC errors
or corrections on the DCode bus.
0x0 R/W1C
00 No error. No errors or corrections reported since reset or the register was last cleared.
01 2-bit error. 2-bit ECC error has been detected and reported on AHB read access.
10 1-bit correction. 1-bit ECC correction has been detected and reported on AHB read access.
11 Reserved.
[26:25] ECCICODE ICode AHB Error ECC Status. Provides details for AHB errors generated due to ECC errors or
corrections on the ICode bus.
0x0 R/W1C
00 No error. No errors or corrections reported since reset or the register was last cleared.
01 2-bit error. 2-bit ECC error has been detected and reported on AHB read access.
10 1-bit correction. 1-bit ECC correction has been detected and reported on AHB read access.
11 Reserved.
[24:20] Reserved Reserved. 0x0 R
[19:17] ECCERRCNT ECC Correction Counter. This counter keeps track of overlapping ECC 1-bit correction reports.
When configured to generate IRQs or AHB errors in the event of an ECC correction event, this
field counts the number of ECC corrections that occur after the first reported correction. The
counter remains at full scale when it overflows and clears automatically when clearing either
the ECCICODE or ECCDCODE status bits.
0x0 R/W1C
[16:15] ECCINFOSIGN ECC Status of Flash Initialization. ECC status after the end of automatic signature check on
information space.
0x0 R
00 No error. No errors reported.
01 2-bit error. One or more 2-bit ECC errors detected during signature check. Signature check
has failed.
10 1-bit error. One or more 1-bit ECC corrections performed during signature check. Signature
check passes if checksum still matches.
11 1-bit and 2-bit error. At least one of each ECC event (1-bit correction and 2-bit error) were
detected during signature check. Signature check fails.
14 INIT Flash Controller Initialization in Progress. Flash controller initialization is in progress. Until this
bit deasserts, AHB accesses stall and APB commands are ignored.
0x0 R
13 SIGNERR Signature Check Failure During Initialization. Indicates an automatic signature check has failed
during flash controller initialization. The register value is valid only after the signature check
has completed.
0x0 R
12 Reserved Reserved. 0x0 R
11 OVERLAP Overlapping Command. This bit is set when a command is requested while another command
is busy. Overlapping commands are ignored.
0x0 R/W1C
[10:9] ECCRDERR ECC IRQ Cause. This field reports the cause of recently generated interrupts. The controller
can be configured to generate interrupts for 1-bit or 2-bit ECC events by writing the appropriate
values to IEN, Bits[7:6]. These bits are sticky high until cleared by user code.
0x0 R/W1C
00 No error.
01 2-bit error. ECC engine detected a noncorrectable 2-bit error during AHB read access.
10 1-bit correction. ECC engine corrected a 1-bit error during AHB read access.
11 1-bit and 2-bit events. ECC engine detected both 1-bit and 2-bit data corruptions, which
triggered IRQs. A single read can only report one type of event. This status indicates that a

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.