Reference Manual ADuCM356
REGISTER DETAILS: GENERAL-PURPOSE TIMERS
analog.com Rev. A | 270 of 312
16-BIT ASYNCHRONOUS LOAD VALUE REGISTERS
Address: 0x40000014, Reset: 0x0000, Name: GPT0_ALOAD
Address: 0x40000414, Reset: 0x0000, Name: GPT1_ALOAD
Address: 0x40000814, Reset: 0x0000, Name: GPT2_ALOAD
Table 348. Bit Descriptions for GPT0_ALOAD, GPT1_ALOAD, GPT2_ALOAD
Bits Bit Name Settings Description Reset Access
[15:0] VALUE 16-Bit Captured Value. GPTx_CAPTURE holds its value until GPTx_CLRINT, Bit 1 is set by user code.
GPTx_CAPTURE is not overwritten even if another event occurs without writing to GPTx_CLRINT, Bit
1. Only use when a synchronous clock source is selected (GPTx_CTL, Bits[6:5] = 00 or if the high
frequency oscillator is clocking both the timer and CPU directly).
0x0000 R
16-BIT TIMER ASYNCHRONOUS VALUE REGISTERS
Address: 0x40000018, Reset: 0x0000, Name: GPT0_ACURCNT
Address: 0x40000418, Reset: 0x0000, Name: GPT1_ACURCNT
Address: 0x40000818, Reset: 0x0000, Name: GPT2_ACURCNT
Table 349. Bit Descriptions for GPT0_ACURCNT, GPT1_ACURCNT, GPT2_ACURCNT
Bits Bit Name Settings Description Reset Access
[15:0] VALUE Counter Value. Reflects the current up or down counter value. Reading GPTx_ACURCNT takes
advantage of having the timer run on PCLK by bypassing clock synchronization logic that is otherwise
required. Only use when a synchronous clock source is selected (GPTx_CTL, Bits[6:5] = 00 or if the high
frequency oscillator is clocking both the timer and CPU directly).
0x0000 R
STATUS REGISTERS
Address: 0x4000001C, Reset: 0x0000, Name: GPT0_STAT
Address: 0x4000041C, Reset: 0x0000, Name: GPT1_STAT
Address: 0x4000081C, Reset: 0x0000, Name: GPT2_STAT
Table 350. Bit Descriptions for GPT0_STAT, GPT1_STAT, GPT2_STAT
Bits Bit Name Settings Description Reset Access
[15:8] Reserved Reserved. 0x0 R
7 PDOK GPTx_CLRINT Synchronization. This bit is set automatically when the user sets GPTx_CLRINT, Bit 0 =
1. This bit is cleared automatically when the clear interrupt request has crossed clock domains and taken
effect in the timer clock domain.
0x0 R
0 The interrupt is cleared in the timer clock domain.
1 GPTx_CLRINT, Bit 0 is being updated in the timer clock domain.
6 BUSY Timer Busy. This bit informs the user that a write to GPTx_CTL is still crossing into the timer clock domain.
Check this bit after writing GPTx_CTL and suppress further writes until this bit is cleared.
0x0 R
0 Timer ready to receive commands to GPTx_CTL.
1 Timer not ready to receive commands to GPTx_CTL.
[5:2] Reserved Reserved. 0x0 R
1 CAPTURE Capture Event Pending. 0x0 R
0 No capture event is pending.
1 A capture event is pending.
0 TIMEOUT Timeout Event Occurred. This bit is set automatically when the value of the counter reaches zero while
counting down or reaches full scale when counting up. This bit is cleared when GPTx_CLRINT, Bit 0 is set
by the user.
0x0 R
To Next Page
Loading...
Need help?
General