Reference Manual ADuCM356
REGISTER DETAILS: POWER MANAGEMENT UNIT
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Table 30. Bit Descriptions for SRAM_INITSTAT (Continued)
Bits Bit Name Settings Description Reset Access
0 Not initialized.
1 Initialization completed.
1 BNK1 Initialization Status of SRAM Bank 1. 0x0 R
0 Not initialized.
1 Initialization completed.
0 BNK0 Initialization Status of SRAM Bank 0. 0x1 R
0 Not initialized.
1 Initialization completed.
POWER MODES REGISTER
Address: 0x400C0A00, Reset: 0x0001, Name: PWRMOD
Table 31. Bit Descriptions for PWRMOD
Bits Bit Name Settings Description Reset Access
[15:4] Reserved Reserved. 0x0 R
3 SEQSLPEN Autosleep Function by Sequencer Command. 0x0 R/W
0 Disables the sequencer autosleep function.
1 Enables the sequencer autosleep function.
2 TMRSLPEN Autosleep Function by Sleep and Wake-Up Timer. 0x0 R/W
0 Disables the sleep and wake-up timer autosleep function.
1 Enables the sleep and wake-up timer autosleep function.
[1:0] PWRMOD Power Mode Control Bits. When read, these bits contain the last power mode value entered by user
code.
0x1 R/W
00, 11 Reserved. Do not enter this mode.
01 Active Mode. Normal working mode. All digital circuits powered up. User can optionally power down
blocks by disabling their input clock.
10 Hibernate Mode. Digital core powered down, most analog die blocks are powered down. Low-power
DACs or references can remain active to bias an external sensor. The high-speed clock is powered
down. Only the low-speed clock is powered up.
KEY PROTECTION FOR PWRMOD REGISTER
Address: 0x400C0A04, Reset: 0x0000, Name: PWRKEY
Table 32. Bit Descriptions for PWRKEY
Bits Bit Name Settings Description Reset Access
[15:0] PWRKEY PWRMOD Key Register. The PWRMOD register is key protected. Two writes to the key are necessary to
change the value in the PWRMOD register: first 0x4859, then 0xF27B. A write to any other register before
writing to PWRMOD returns the protection to the lock state.
0x0 R/W
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