Reference Manual ADuCM356
POWER MANAGEMENT UNIT
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power-on reset (POR) can reset the debug logic. Therefore, the
device must be power cycled after using the serial wire debug
with an application code containing the wait for interrupt (WFI)
instruction.
Active Mode, Mode 0
The system is fully active. Memories and all user enabled periph-
erals are clocked, and the Arm Cortex-M3 processor executes
instructions. The Arm Cortex-M3 processor manages its internal
clocks and can be in a partial clock gated state. This clock gating
affects only the internal Arm Cortex-M3 processing core. Automatic
clock gating is used on all blocks except the I
2
C, UART, and
general-purpose timers. These blocks are manually clock gated
using the CLKG CTL5 register for the digital die and the CLKEN1
register for the analog die.
The user code can use a WFI command to put the Arm Cortex-M3
processor into sleep mode. The processor is independent of the
power mode settings of the PMU.
Writing 1 to CLKG CTL5, Bits[5:0] or AFE CLKEN1, Bits[9:0] stops
the corresponding clock to peripherals. For the digital die peripher-
als, after the clock stops, if the user or software accesses any
register in that peripheral, the clock is automatically enabled. In
addition, writing 0 to these bits in the CLKG CTL5 or AFE CLKEN1
registers enables the corresponding clock to the peripheral.
Chip power-up with the LDO regulator is on by default on both dice.
The buck regulator can be enabled to save power consumption by
writing 1 to the PMG0 CTL1, Bit 0. When enabled, the input to the
on-chip 1.2 V LDO regulator is the buck converter output, which is
typically 1.6 V.
When the ADuCM356 wakes up from any of the low-power modes,
the device returns to Mode 0.
Flexi Mode, Mode 1 (Digital Die Only)
In flexi mode, the system gates the clock to the Arm Cortex-M3
core after the Arm Cortex-M3 enters power-down by executing the
WFI instruction. The rest of the system remains active, and no
instructions can be executed. However, DMA transfers can continue
to occur between peripherals and memories. The Arm Cortex-M3
processor, RCLK (clock to flash), is active, and the device wakes up
using the nested vectored interrupt controller (NVIC).
Hibernate Mode, Mode 2
To enter hibernate mode, the user must first configure the analog
die for hibernate by setting ALLON PWRMOD, Bits[1:0] = 10, and
then, the user can place the digital die into hibernate mode. To
minimize current consumption, configure unused digital GPIO pins
as tristate on both dice.
On the digital die, in hibernate mode, the Arm Cortex-M3 and all
digital peripherals are turned off. The SRAM can be programmed to
retain up to 32 kB. The user can select the following:
â–º The amount of SRAM to retain. This amount is in addition to
the 8 kB of SRAM always retained in the hibernate mode. This
selection is controlled using SRAMRET, Bits[1:0].
â–º Control battery monitoring during hibernate mode. The regulated
1.2 V supply is always monitored to guarantee that data is never
corrupted by the supply going below the minimum retention
voltage. If the regulated supply falls below 1 V, the chip resets
before any data is corrupted. Though the regulated supply is al-
ways monitored, there is an option to also monitor the AVDD_DD
pin (2.8 V to 3.6 V supply) in hibernate mode by clearing PMG0
PWRMOD, Bit 3 = 0.
On the analog die, in hibernate mode, the AFE high-speed clock
circuits are powered down, causing all blocks clocked by these
circuits to enter a low-power, clock gated state. After setting ALLON
PWRMOD, Bits[1:0] = 10, do not read back the value of the register
because this read can halt the entry of the analog die into hibernate
mode.
CODE EXAMPLES
Enter Power Saving Mode
The following function configures the analog die operating mode:
uint32_t AfePwrCfg(uint16_t iMode)
{
// PSWFULLCON[14:13]= [11]b
//Close switches NL and NL2. PSWFULLâ–º
CON[11:10]= [11]b
pADI_AFE-> PSWFULLCON|=0x6C00; // Close
PL2, PL1, P12, P11 switches to tie HSTIA N and
D
//terminals to 1.8 V LDO
pADI_ALLON->PWRKEY = 0x4859;
pADI_ALLON->PWRKEY = 0xF27B;
pADI_ALLON->PWRMOD = (pADI_ALLON-
>PWRMOD&(~BITM_ALLON_PWRMOD_PWRMOD))|iMode;
//=========================================
// IMPORTANT
// If Chip is going into hibernate mode, you
// cannot read PWRMOD after configuring it.
// For safety reasons, return value set
// to 0 directly.
//=========================================
//return pADI_ALLON->PWRMOD;
return 0;
}
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