Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: DMA
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Table 208. Bit Descriptions for PRI_SET
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Configure Channel Priority. This register enables the user to configure a DMA channel to use the
high priority level. Reading the register returns the status of the channel priority mask. Each bit
of the register represents the corresponding channel number in the DMA controller. This register
returns the channel priority mask status or sets the channel priority to high. Bit 0 corresponds to
DMA Channel 0. Bit M – 1 corresponds to DMA Channel M – 1.
0x000000 W
0 When read as 0, DMA Channel C uses the default priority level. When written as 0, no effect. Use
the PRI_CLR register to set Channel C to the default priority level.
1 DMA Channel C uses a high priority level.
CHANNEL PRIORITY CLEAR REGISTER
Address: 0x4001003C, Reset: 0x00000000, Name: PRI_CLR
Table 209. Bit Descriptions for PRI_CLR
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHPRICLR Configure Channel for Default Priority Level. This write only register enables the user to configure a
DMA channel to use the default priority level. Each bit of the register represents the corresponding
channel number in the DMA controller. Set the appropriate bit to select the default priority level for
the specified DMA channel. Bit 0 corresponds to DMA Channel 0. Bit M – 1 corresponds to DMA
Channel M – 1.
0x000000 W
0 No effect. Use the PRI_SET register to set Channel C to the high priority level.
1 Channel C uses the default priority level.
BUS ERROR CLEAR REGISTER
Address: 0x40010048, Reset: 0x00000000, Name: ERR_CLR
Table 210. Bit Descriptions for ERR_CLR
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Bus Error Status. This register is used to read and clear the DMA bus error status. The error status
is set if the controller encountered a bus error while performing a transfer or when it reads an
invalid descriptor (whose cycle control is 0b000). If a bus error occurs or an invalid cycle control is
read on a channel, that channel is automatically disabled by the controller. The other channels are
unaffected. Write 1 to clear bits.
0x000000 R/W1C
0 When read, no bus error or an invalid cycle control has occurred. When written, no effect.
1 When read, a bus error or invalid cycle control is pending. When written, bit is cleared.
PER CHANNEL BUS ERROR REGISTER
Address: 0x4001004C, Reset: 0x00000000, Name: ERRCHNL_CLR
Table 211. Bit Descriptions for ERRCHNL_CLR
Bits Bit Name Settings Description Reset Access
[31:24] Reserved Reserved. 0x00 R
[23:0] CHAN Per Channel Bus Error Status and Per Channel Bus Error Clear. This register is used to read and
clear the per channel DMA bus error status. The error status is set if the controller encountered
a bus error while performing a transfer. If a bus error occurs on a channel, that channel is
automatically disabled by the controller. The other channels are unaffected. Write 1 to clear bits.
0x000000 R/W1C
0 When read as 0, no bus error has occurred. When written as 0, no effect.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English