Analog Devices ADuCM356 User Manual

Reference Manual ADuCM356
REGISTER DETAILS: SPI0/SPI1
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Table 310. Bit Descriptions for SPI0_CTL, SPI1_CTL
Bits Bit Name Settings Description Reset Access
15 Reserved Reserved. 0x0 R
14 CSRST Reset Mode for Chip Select Error Bit. 0x0 R/W
0 The bit counter continues from where it stopped. The SPI can receive the remaining bits when the chip
select is asserted and user code must ignore the SPIx_STAT, Bit 12 interrupt.
1 The bit counter is reset after a chip select error condition and the user code is expected to clear SPIx_CTL,
Bit 0. Set this bit for a recovery after a chip select error.
13 TFLUSH SPI Transmit FIFO Flush Enable. 0x0 R/W
0 Disable transmit FIFO flushing.
1 Flush the transmit FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this
bit is left high, either the last transmitted value or 0x00 is transmitted depending on the ZEN bit. Any writes
to the transmit FIFO are ignored while this bit is set.
12 RFLUSH SPI Receive FIFO Flush Enable. 0x0 R/W
0 Disable receive FIFO flushing.
1 Flush the receive FIFO. This bit does not clear itself and must be toggled if a single flush is required. If this
bit is set, all incoming data is ignored and no interrupts are generated. If set and the TIM bit = 0, a read of
the receive FIFO initiates a transfer.
11 CON Continuous Transfer Enable. 0x0 R/W
0 Disable continuous transfer. Each transfer consists of a single 8-bit serial transfer. If valid data exists in the
SPIx_TX register, a new transfer is initiated after a stall period of one serial clock cycle.
1 Enable continuous transfer. In initiator mode, the transfer continues until no valid data is available in the
transmit FIFO. Chip select is asserted and remains asserted for the duration of each 8-bit serial transfer
until FIFO is empty.
10 LOOPBACK Loopback Enable. 0x0 R/W
0 Normal mode.
1 Connect MISO to MOSI and test software.
9 OEN Target MISO Output Enable. 0x0 R/W
0 Disable the output driver on the MISO pin. The MISO pin is open circuit when this bit is clear.
1 MISO operates as normal.
8 RXOF SPI Receive Overflow Overwrite Enable. 0x0 R/W
0 The new serial byte received is discarded.
1 The valid data in the receive register is overwritten by the new serial byte received.
7 ZEN Transmit Zeros Enable. 0x0 R/W
0 Transmit the last transmitted value when there is no valid data in the transmit FIFO.
1 Transmit 0x00 when there is no valid data in the transmit FIFO.
6 TIM SPI Transfer and Interrupt Mode. 0x0 R/W
0 Initiate transfer with a read of the SPIx_RX register. An interrupt only occurs when the receive FIFO is full.
1 Initiate transfer with a write to the SPIx_TX register. An interrupt only occurs when the transmit FIFO is
empty.
5 LSB LSB First Transfer Enable. 0x0 R/W
0 MSB transmitted first.
1 LSB transmitted first.
4 WOM SPI Wire-OR’ed Mode. 0x0 R/W
0 Normal output levels.
1 Enables open circuit data output enable. External pull-up resistors required on data out pins.
3 CPOL Serial Clock Polarity. 0x0 R/W
0 Serial clock idles low.
1 Serial clock idles high.
2 CPHA Serial Clock Phase Mode. 0x0 R/W
0 Serial clock pulses at the end of each serial bit transfer.

Analog Devices ADuCM356 Specifications

General

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Summary

PREFACE

SCOPE

Provides a detailed description of the functionality and features of the ADuCM356.

CLOCKING ARCHITECTURE

DIGITAL DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the digital die system clock.

ANALOG DIE CLOCK FEATURES

Details the clock sources, dividers, and gating for the analog die system clock.

POWER MANAGEMENT UNIT

Active Mode

Describes the fully active operating mode where the Arm Cortex-M3 executes from flash and SRAM.

Flexi Mode

Describes the mode where the Arm Cortex-M3 is disabled, allowing peripherals to operate.

Hibernate Mode

Describes the low-power mode where the digital core and most analog blocks are powered down.

SYSTEM RESETS

DIGITAL DIE RESET OPERATION

Explains the reset sources and operation for the digital die, including software resets.

PROGRAMMING, PROTECTION, AND DEBUG

Debug Features

Details the SWD port, flash patch breakpoints, and data watchpoint/trigger units for debugging.

SYSTEM EXCEPTIONS AND PERIPHERAL INTERRUPTS

CORTEX-M3 AND FAULT MANAGEMENT

Describes the system exceptions and fault handling features integrated with the Cortex-M3 processor.

ANALOG DIE CIRCUITRY SUMMARY

ADC, HIGH-SPEED DAC, AND ASSOCIATED AMPLIFIERS OPERATING MODE CONFIGURATION

Configures the operating modes for ADC, High-Speed DAC, and associated amplifiers.

ADC CIRCUIT

ADC CIRCUIT FEATURES

Lists the key features of the ADuCM356's fast multichannel, 16-bit ADC.

LOW-POWER POTENTIOSTAT AMPLIFIERS AND LOW-POWER TIAS

LOW-POWER POTENTIOSTAT AMPLIFIERS

Details the two low-power potentiostat amplifiers for setting external sensor bias voltage.

HIGH-SPEED DAC CIRCUITS

HIGH-SPEED DAC OUTPUT SIGNAL GENERATION

Explains how to generate high-speed DAC output voltage via direct write or waveform generator.

PROGRAMMABLE SWITCHES CONNECTING THE EXTERNAL SENSOR TO THE HIGH-SPEED DAC AND HIGH-SPEED TIA

DX SWITCHES

Selects pins for the high-speed DAC excitation amplifier output, used for impedance measurements.

SEQUENCER

SEQUENCER COMMANDS

Describes the two types of commands: write commands and timer commands (wait, timeout).

SLEEP AND WAKE-UP TIMER

CONFIGURING A DEFINED SEQUENCE ORDER

Defines the order of sequence execution periodically using the SEQORDER register.

USE CASE CONFIGURATIONS

HIBERNATE MODE WHILE MAINTAINING A DC BIAS TO THE SENSOR

Details setup for hibernate mode while maintaining sensor bias voltage.

DMA CONTROLLER

DMA FEATURES

Lists the features of the ADuCM356's dedicated and independent DMA channels.

FLASH CONTROLLER

SUPPORTED COMMANDS

Summarizes the commands supported by the flash controller for read, write, erase, and signature operations.

REGISTER DETAILS: FLASH CACHE CONTROLLER (FLCC)

COMMAND REGISTER

Allows execution of specified flash commands like write, erase, abort, and signature generation.

DIGITAL INPUTS AND OUTPUTS

DIGITAL INPUTS AND OUTPUTS OPERATION

Explains how to configure, read, and write digital input and output pins.

I2C SERIAL INTERFACE

I2C OPERATION

Details the steps required to run the I2C peripheral, including startup and modes.

SERIAL PERIPHERAL INTERFACES

SPI OPERATION

Describes the operation of the SPI interface, including initiator and target modes.

REGISTER SUMMARY: SPI0/SPI1

STATUS REGISTERS

Provides status information for SPI0 and SPI1, including ready, overflow, and error conditions.

REGISTER DETAILS: UART

INTERRUPT ENABLE REGISTER

Configures which interrupt sources generate an interrupt for the UART.

DIGITAL DIE GENERAL-PURPOSE TIMERS

GENERAL-PURPOSE TIMER OPERATIONS

Explains the operation of timers in free running mode and periodic mode.

REGISTER SUMMARY: ANALOG DIE GENERAL-PURPOSE TIMERS

CONTROL REGISTER

Controls timer operation, including clock source, mode, and event selection.

REGISTER DETAILS: DIGITAL DIE WAKE-UP TIMER

STATUS 0 REGISTER

Provides status information for WUT operation, including synchronization and pending writes.

CYCLIC REDUNDANCY CHECK

CRC OPERATING MODES

Details the core access and DMA access modes for CRC calculation.

REGISTER SUMMARY: CRC

CRC CONTROL REGISTER

Controls the CRC peripheral, including enabling, mirroring, and calculation order.

HARDWARE DESIGN CONSIDERATIONS

SERIAL WIRE DEBUG INTERFACE

Describes the SWD interface for debugging and programming, replacing JTAG.