Reference Manual ADuCM356
FLASH CONTROLLER
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User Key
This key serves to prevent accidental access to some flash features and addresses. The key value is 0x676C7565. This key must be entered
to run protected user commands (erase page, sign, mass erase, and abort) or to enable write access to the UCFG register. When entered, the
key remains valid until an incorrect value is written to the key register, or a command is written to the CMD register. When any command is
requested, this key is automatically cleared. If this key is entered to enable write access to the UCFG register, it is recommended to clear the
key immediately after updating the registers.
ECC
The flash controller provides ECC-based error detection and correction for flash reads. ECC is enabled by default for information space, and
thus provides assurance that flash initialization functions work properly. Information space signature check unconditionally considers ECC. The
flash controller uses an 8-bit Hamming modified code to correct 1-bit errors or detect 2-bit errors for any dual word, 64-bit flash data access.
When enabled, the ECC engine is active during signature checks (refer to the Protection and Integrity section). User code can request a
signature check of the entirety of user space and then check STAT, Bits[8:7] to determine if any single or dual bit data corruptions are present in
user space.
Defaults and Configuration
In user space, ECC is off by default but can be selectively enabled by using the user code. Enabling ECC requires setting ECC_CFG, Bit
0. When enabled, ECC can apply to the entirety of user space or can be configured to apply only to a limited range. A single page address
pointer (ECC_CFG, Bits[31:8]) is used to define the start address for ECC. All flash addresses from the start page through the top of user space
(inclusive) have ECC enabled when ECC_CFG, Bit 0 is set.
ECC errors can be optionally reported as bus errors for ICode or DCode reads or can generate interrupts. Independent error reporting options
are available for 1-bit corrections and 2-bit error detections by writing IEN, Bits[7:6] and IEN, Bits[5:4].
Error Handling
The impact of ECC errors during the information space signature check is described in the Signatures section. On any read operation, if the
ECC engine observes a 1-bit error, the error is corrected automatically. In this case, the 1-bit error is either in the ECC byte itself or in the
64-bit dual word being read by the user. If a 2-bit error is observed, the ECC engine can only report the detection event. 2-bit errors cannot be
corrected.
Depending on when the read happens (for example, during an ICode or DCode read, or as part of a built in command such as a signature
check), appropriate flags are set in the status register. See the Status Register section for details.
If interrupt generation is enabled in IEN, Bits[7:6] or IEN, Bits[5:4], the source address of the ECC error causing the interrupt is available in the
ECC_ADDR register for the interrupt service routine to read.
ECC Errors During Execution of Sign Command
ECC errors observed during signature checks generate the appropriate status register flags after completion, but do not populate the
ECC_ADDR register.
Concurrent Errors
If ECC errors occur on DCode and ICode simultaneously (for example, from an ICode prefetch match and a DCode flash read), ECC error
status information is prioritized. In first priority, 2-bit ECC errors are given priority over 1-bit ECC errors or corrections. For example, if a 2-bit
ECC error is observed on a DCode read in the same cycle as a 1-bit ECC error or correction on an ICode read, the ECC error status is updated
for DCode only.
In second priority, ICode is given priority over DCode. For example, if a 2-bit error is observed on an ICode read and a DCode read in the same
cycle, the ECC error status is updated for ICode only.
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