Reference Manual ADuCM356
I
2
C SERIAL INTERFACE
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the current read count. The addition of + 1 signifies that there is
some room for the completion. If the newly programmed value
is less than the current count, the I
2
C initiator receives until
the current count overflows and reaches the programmed count.
When this overflow occurs, the transfer ends after receiving the
next byte. When the transaction complete interrupt is received,
the core disables the initiator by clearing MCTL, Bit 0.
â–º I
2
C is an initiator and is transmitting data. The software flushes
the transmit FIFO by setting STAT, Bit 9 and disables the trans-
mit request by clearing MCTL, Bit 5. When the transmit request
is disabled, the current transfer ends after transmitting the byte
in progress. When the transaction complete interrupt is received,
the software clears MCTL, Bit 0. Disabling the initiator before
completion can cause the bus to stall indefinitely.
â–º I
2
C is a target and is receiving data. The software sets SCTL,
Bit 7, giving a no acknowledge for the next communication, after
which the external initiator must stop. On receiving the stop
interrupt, the core disables the target by clearing SCTL, Bit 0.
â–º I
2
C is a target and is transmitting data. After the target transmits
starts, it cannot no acknowledge any further transactions, be-
cause the acknowledge is driven only by the initiator. Therefore,
the target transmit must wait until the external initiator issues a
stop condition. After receiving the stop interrupt, the target can
be disabled. However, if the target must be disabled immediately,
such an action can only be performed at the cost of wrong data
being transmitted (all 0xFFs) because the I2C_SDA line is not
driven anymore and is pulled up during data phase. The bus
does not stall in this case.
DMA Requests
Four DMA channels are provided to service the I
2
C initiator and
target. The DMA enabled bits are provided in the target control
register and in the initiator control register.
I
2
C Pins when ADuCM356 is Unpowered
When the ADuCM356 is not powered up, do not apply logic high
signals to any digital pins. The maximum voltage that can be
applied to a digital input pin at any time is DVDD + 0.3 V. If this
limit is exceeded, the ESD protection diodes start to conduct to
ground. If the ADuCM356 is unpowered but the I
2
C bus pins are at
a logic high, the ADuCM356 pin protection structure pulls I2C_SCL
and I2C_SDA toward ground, causing issues for devices that are
powered on the bus.
It is recommended that all devices with an I
2
C bus (including the
ADuCM356) are fully powered up before any communications is
started on the bus.
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