Reference Manual ADuCM356
I
2
C SERIAL INTERFACE
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register contains the remaining eight bits of the 10-bit address. The
ID2 register and ID3 register can still be programmed with 7-bit
addresses.
The initiator communicates to a 10-bit address target using the
ADR1 register and ADR2 registers. The format is described in
Figure 58. To perform a read from a target with a 10-bit address,
the initiator must first send a 10-bit address with the R/W bit
cleared. It must then generate a repeated start and send only the
first byte of the address with the R/W bit set. A repeated start is
generated by writing to the ADR1 register while the initiator is still
busy.
Figure 58. 10-Bit Address Format
A repeated start condition occurs when a second start condition is
sent to a target without a stop condition being sent in between. This
sequence allows the initiator to reverse the direction of the transfer
by changing the R/W bit without having to give up control of the
bus. An example of a transfer sequence is shown in Figure 59. This
sequence is generally used in cases where the ability of the register
to be read is established by the first data sent to the device.
Figure 59. I
2
C Repeated Start Sequence
On the target side, an interrupt is generated (if enabled in the SCTL
register) when a repeated start and a target address are received.
This sequence is differentiated from receiving a start and target
address by using the start and REPSTART status bits in the SSTAT
MMR.
On the initiator side, the initiator generates a repeated start if
the ADR1 register is written while the initiator is still busy with a
transaction. After the I
2
C state machine has started to transmit the
device address, it is safe to write to the ADR1 register.
For example, if a transaction involving a write, a repeated start,
and then a read/write is required, write to the ADR1 register either
after the state machine starts to transmit the device address or after
the first MTXREQ interrupt is received. When the transmit FIFO
empties, a repeated start is generated. Similarly, if a transaction
involving a read, a repeated start, and then a read/write is required,
write to the first initiator address byte register, ADR1, either after
the state machine starts to transmit the device address or after the
first MRXREQ interrupt is received. When the requested receive
count is reached, a repeated start is generated.
I
2
C Clock Control
A PCLK clocks the I
2
C peripherals. CTL5, Bit 5 and CTL5, Bit 3
must be cleared to enable the clock to the I
2
C block. The frequency
of PCLK is determined by CTL1, Bits[13:8]. The I
2
C initiator in
the system generates the serial clock for a transfer. The initiator
channel can be configured to operate in fast mode (400 kHz) or
standard mode (100 kHz).
The bit rate is defined in the DIV MMR as follows:
f
SCL
= f
I2CCLK
/(Low + High + 3)
(23)
where:
f
SCL
is the I
2
C baud rate.
f
I2CCLK
is the PCLK frequency.
Low is the low period of the clock, DIV[7:0].
High is the high period of the clock, DIV[15:8].
High = REQD_HIGH_TIME/PCLK_PERIOD – 2
where:
REQD_HIGH_TIME is the required high time period.
PCLK_PERIOD is the PCLK period.
Low = REQD_LOW_TIME/PCLK_PERIOD – 1
where REQD_LOW_TIME is the required low time period.
For 100 kHz SCL operation with a low time of 5 µs, a high time of 5
µs, and a PCLK frequency of 26 MHz,
High = (5 µs/(1/26,000,000)) − 2 = 128 = 0x80
(24)
Low = (5 µs/(1/26,000,000)) − 1 = 129 = 0x81
(25)
f
SCL
= 26,000,000/(128 + 129 + 3) = 100 kHz
(26)
Resetting the I
2
C Block
Three steps are needed to reset the I
2
C block. Do not reset the I
2
C
peripheral on two consecutive communication sequences.
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