Reference Manual ADuCM356
SEQUENCER
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Determine the number of commands in a sequence by reading the
SEQxINFO register, Bits[26:16].
The command memory is unidirectional. The host microcontroller
specifies the destination address of the command by writing to the
CMDFIFOWADDR register and writes the command contents to
the CMDFIFOWRITE register. The sequencer reads the commands
from memory for execution.
There are a number of interrupts associated with the command
FIFO, including the FIFO threshold interrupt, the FIFO empty inter-
rupt, and the FIFO full interrupt. Refer to the AFE Interrupts section
for more information.
Loading Sequences
The sequence commands are written to the SRAM by writing to two
registers. The address in SRAM for the command is written to the
CMDFIFOWADDR register. The command content is written to the
CMDFIFOWRITE register. When all commands are written to the
SRAM, write to the SEQxINFO registers to set the SEQ0 to SEQ3
information sequences.
Each information sequence from SEQ0 to SEQ3 requires a start
address in SRAM and a total number of commands for that se-
quence. The number of commands is written to the SEQxINFO
register, Bits[26:16]. The start address is written to the SEQxINFO
register, Bits[10:0]. Ensure that there is no overlap between the four
sequences. There is no hardware mechanism in place to warn the
user of overlapping sequences.
The interrupt sources associated with the sequencer include the
following:
â–º Sequence timeout error.
â–º Sequencer timeout command finished.
â–º End of sequence interrupt. For this interrupt to be asserted,
the SEQCON register, Bit 0, must be cleared at the end of the
sequencer command.
Data FIFO
The data FIFO provides a buffer for the output of the analog and
DSP blocks before the FIFO is read by the external controller.
The memory available for the data FIFO can be selected in the
DATA_MEM_SEL bits in the CMDDATACON register. The available
memory options are 2 kB, 4 kB, and 6 kB. The data FIFO and
command memory share the same block of 6 kB SRAM. Therefore,
ensure that there is no overlap between the command memory and
the data FIFO.
The data FIFO can be configured in FIFO mode or stream mode via
the CMDDATACON register, Bits[11:9]. In stream mode, when the
FIFO is full, old data is discarded to make room for new data. In
FIFO mode, when the FIFO is full, new data is discarded. Do not let
the FIFO overflow when in FIFO mode. If there is overflow, all new
data are lost.
The data FIFO is always unidirectional. A selectable source in the
AFE block writes data and the external microcontroller reads data
from the DATAFIFORD register (see Table 220).
Select the data source for the data FIFO in the FIFOCON register,
Bits[15:13] (see Table 219). The available source options include
ADC data, DFT result, sinc2 filter result, and statistic block mean
result.
The interrupt flags associated with the data FIFO include empty,
full, overflow, underflow, and threshold. These interrupts are user
readable using the INTCFLAGx registers (see the AFE Interrupts
section for more details). Each flag has an associated maskable
interrupt.
The overflow and underflow flags only activate for one clock period.
The data FIFO is enabled by writing a 1 to the FIFOCON register,
Bit 11. The data FIFO threshold value is set by writing to the
DATAFIFOTHRES register. At any time, the host microcontroller
can read the number of words in the data FIFO by reading the
FIFOCNTSTA register, Bits[26:16].
Reading data from the data FIFO when the FIFO is empty re-
turns 0x00000000. The underflow flag, the FLAG27 bit, in the
INTCFLAGx register is also asserted.
Data FIFO Word Format
The format of data FIFO words is shown in Figure 32. Each word
in the data FIFO is 32 bits. The seven MSBs are the ECC required
for functional safety applications. Bits[24:23] of the data FIFO word
form the sequence identification (ID) and indicate which sequence,
from SEQ0 to SEQ3, the result came from.
Bits[22:16] of the data FIFO word contain the channel ID and
indicate the source for the data (see Table 153).
The 16 LSBs of the data FIFO word are the actual data (see Figure
32).
When the data source is the DFT result, the data is 18 bits wide
and is in twos complement format. The format is shown in Figure
33. The channel ID is five bits wide, with 5'b11111 indicating the
DFT results.
Sequencer and the Sleep and Wake-Up Timer
See the Sleep and Wake-Up Timer section for more information.
Sequencer Conflicts
If a conflict between sequences arises, for example, when SEQ0 is
running and the SEQ1 request arrives, SEQ1 is ignored and SEQ0
completes. An interrupt is generated to indicate that the Sequence
1 is ignored.
Reading back registers does not cause resource conflicts. Writes to
the MMRs by the processor are not allowed when the sequencer
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