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Reference Manual ADuCM356

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Table 316. Bit Descriptions for SPI0_FLOW_CTL, SPI1_FLOW_CTL (Continued)

Bits Bit Name Settings Description Reset Access

[1:0] MODE Flow Control Mode. Flow control configuration for data reads. When the P0.3 signal is used for flow

control, P0.3 can be any control signal that is tied to this P0.3 input of the SPI module.

0x0 R/W

00 Flow control is disabled.

01 Flow control is based on timer SPIx_WAIT_TMR.

10 Flow control is based on P0.3 signal.

11 Flow control is based on MISO pin.

Preface1
Scope1
Table of Contents2
Using the Aducm356 Hardware Reference Manual9
- Number Notations9
- Register Access Conventions9
Aducm356 Overview10
- Main Features of the Aducm35610
Clocking Architecture12
- Clocking Architecture Operation12
- Required Clock Ratio between Digital die and Analog die System Clocks12
- Digital die Clock Features12
- Analog die Clock Features12
- Clock Gating13
- Connecting AFE die Clock to Digital die Clock Input13
Register Summary: Clock Architecture15
Register Details: Clock Architecture16
- Key Protection for CTL Register16
- Oscillator Control Register16
- Clock Control 0 Register16
- Clock Dividers Register17
- User Clock Gating Control Register17
- Clocking Status Register18
- Clock Divider Configuration Register18
- Clock Gate Enable Register19
- Clock Select Register19
- GPIO Clock Mux Select to GPIO1 Pin Register20
- Key Protection for CLKCON0 Register20
- Clock Control of Low-Power TIA Chop, Watchdog, and Wake-Up Timers Register20
- Key Protection for OSCCON Register21
- Oscillator Control Register21
- High-Power Oscillator Configuration Register22
- Power Mode Configuration Register22
Power Management Unit23
- Power Management Unit Features23
- Power Management Unit Operation23
- Code Examples24
- Monitor Voltage Control25
Register Summary: Power Management Unit27
Register Details: Power Management Unit28
- Power Supply Monitor Interrupt Enable Register28
- Power Supply Monitor Status Register28
- Power Mode Register29
- Key Protection for PWRMOD and SRAMRET Register29
- Control for Retention SRAM During Hibernate Mode Register29
- High-Power Buck Control Register30
- Control for SRAM Parity and Instruction SRAM Register30
- Initialization Status Register31
- Power Modes Register32
- Key Protection for PWRMOD Register32
Arm Cortex-M3 Processor33
- Arm Cortex-M3 Processor Features33
- Arm Cortex-M3 Processor Operation33
- Arm Cortex-M3 Processor Related Documents34
System Resets35
- Digital die Reset Operation35
Register Summary: System Resets36
Register Details: System Resets37
- Digital die Reset Status Register37
- Always on Reset Status Register37
- Analog die Status Register37
Programming, Protection, and Debug38
- Booting38
- Security Features38
- Safety Features38
System Exceptions and Peripheral Interrupts39
- Cortex-M3 and Fault Management39
- Interrupt Sources from the Analog die41
- Clearing Analog die Interrupt Sources42
- Cortex-M3 NVIC Register List42
- External Interrupt Configuration43
Register Summary: System Exceptions and Peripheral Interrupts44
Register Details: System Exceptions and Peripheral Interrupts45
- External Interrupt Configuration 0 Register45
- External Wake-Up Interrupt Status Register46
- External Interrupt Clear Register46
- Nonmaskable Interrupt Clear Register46
- Analog die Interrupt Enable Register46
Analog die Circuitry Summary48
- ADC, High-Speed DAC, and Associated Amplifiers Operating Mode Configuration48
- System Bandwidth Configuration48
Register Summary: Analog die Circuitry50
Register Details: Analog die Circuitry51
- AFE Configuration Register51
ADC Circuit53
- ADC Circuit Overview53
- ADC Circuit Features53
- ADC Circuit Operation54
- ADC Transfer Function54
- ADC Low-Power Current Input Channels55
- ADC Input Circuit55
- ADC Postprocessing Filter Options55
- Averaging, Statistics, and Outlier Detection Options57
- Internal Temperature Sensor Channels57
- ADC Initialization58
- ADC Calibration58
- ADC Digital Signal Processor (DSP) Built in Self Test59
- Voltage Reference Options60
Register Summary: ADC Circuit61
Register Details: ADC Circuit63
- ADC Configuration Register63
- ADC Output Filters Configuration Register64
- Raw Result Register65
- DFT Result, Real Part Register66
- DFT Result, Imaginary Part Register66
- Sinc2 and Supply Rejection Filter Result Register66
- Temperature Sensor 0 Result Register66
- Analog Capture Interrupt Enable Register66
- Analog Capture Interrupt Register67
- AFE DSP Configuration Register68
- Temperature Sensor 0 Configuration Register69
- High-Power and Low-Power Buffer Control Register69
- Number of Repeat ADC Conversions Register70
- Buffer Configuration Register70
- Calibration Lock Register71
- Offset Calibration Low-Power TIA0 Channel Register71
- Gain Calibration for Low-Power TIA0 Channel Register71
- Offset Calibration Low-Power TIA1 Channel Register72
- Gain Calibration for Low-Power TIA1 Channel Register72
- Offset Calibration High-Speed TIA Channel Register72
- Gain Calibration for High-Speed TIA Channel Register73
- Offset Calibration Voltage Channel (PGA Gain = 1) Register73
- Gain Calibration Voltage Input Channel (PGA Gain = 1) Register73
- Offset Calibration Voltage Channel (PGA Gain = 1.5) Register73
- Gain Calibration Voltage Input Channel (PGA Gain = 1.5) Register74
- Offset Calibration Voltage Input Channel (PGA Gain = 2) Register74
- Gain Calibration Voltage Input Channel (PGA Gain = 2) Register74
- Offset Calibration Voltage Input Channel (PGA Gain = 4) Register75
- Gain Calibration Voltage Input Channel (PGA Gain = 4) Register76
- Offset Calibration Voltage Input Channel (PGA Gain = 9) Register76
- Gain Calibration Voltage Input Channel (PGA Gain = 9) Register76
- Offset Calibration Temperature Sensor Channel 0 Register76
- Gain Calibration Temperature Sensor Channel 0 Register77
- Minimum Value Check Register77
- Minimum Slow Moving Value Register77
- Maximum Value Check Register77
- Maximum Slow Moving Register78
- Delta Check Register78
- Statistics Module Configuration Register78
- Mean Output Register78
- Key Access for DSPUPDATEEN Register80
- Digital Logic Test Enable Register80
- Temperature Sensor 1 Control Register80
Low-Power Potentiostat Amplifiers and Low-Power Tias81
- Low-Power Potentiostat Amplifiers81
- Low-Power Tias81
- Low-Power Dacs84
Register Summary: Low-Power Tia/Potentiostat and Dac Circuits88
Register Details: Low Power Tia/Potentiostat and DAC Circuits89
- Low-Power TIA Control Bits Channel 0 Register89
- Low-Power TIA Switch Configuration for Channel 0 Register90
- Low-Power TIA Control Bits Channel 1 Register91
- Low-Power TIA Switch Configuration for Channel 1 Register93
- LPDAC0 Data out Register94
- LPDAC0 Switch Control Register94
- LPDAC0 Control Register95
- LPDAC1 Data out Register96
- LPDAC1 Switch Control Register96
- LPDAC1 Control Register96
- Low-Power Reference Control Register97
High-Speed TIA Circuits98
- Key Features98
- Using DE0 and DE1 Inputs with the High-Speed TIA99
- External RTIA Selection100
Register Summary: High-Speed TIA Circuits101
Register Details: High-Speed TIA Circuits102
- High-Speed RTIA Configuration Register102
- DE1 High-Speed TIA Resistor Configuration Register102
- DE0 High-Speed TIA Resistor Configuration Register102
- High-Speed TIA Amplifier Configuration Register103
High-Speed DAC Circuits104
- High-Speed DAC Output Signal Generation104
- High-Speed DAC Core Power Modes104
- Recommended Configuration in Hibernate Mode105
- High-Speed DAC Filter Options105
- High-Speed DAC Output Attenuation Options105
- Coupling an AC Signal from High-Speed DAC Onto the DC Level Set by Low-Power DAC106
- Avoiding Incoherency Errors between Excitation and Measurement Frequencies During Impedance Measurements106
- Calibrating the High-Speed DAC106
Register Summary: High-Speed DAC Circuits108
Register Details: High-Speed DAC Circuits109
- High-Speed DAC Configuration Register109
- Direct Write to DAC Output Control Value Register109
- DAC DC Buffer Configuration Register109
- DAC Gain Register109
- DAC Offset with Attenuator Enabled (Low-Power Mode) Register110
- DAC Offset with Attenuator Disabled (Low-Power Mode) Register110
- DAC Offset with Attenuator Enabled (High-Power Mode) Register110
- DAC Offset with Attenuator Disabled (High-Power Mode) Register111
- Waveform Generator Configuration Register111
- Waveform Generator for Sinusoid Frequency Control Word Register111
- Waveform Generator for Sinusoid Phase Offset Register112
- Waveform Generator for Sinusoid Offset Register112
- Waveform Generator for Sinusoid Amplitude Register112
Programmable Switches Connecting the External Sensor to the High-Speed DAC and High-Speed TIA113
- DX Switches113
- Px Switches113
- Nx Switches113
- Tx Switches113
- Options for Controlling All Switches113
Register Summary: Programmable Switches116
Register Details: Programmable Switches117
- Switch Matrix Configuration Register117
- DX Switch Matrix Full Configuration Register118
- Nx Switch Matrix Full Configuration Register119
- Px Switch Matrix Full Configuration Register120
- Tx Switch Matrix Full Configuration Register121
- DX Switch Matrix Status Register122
- Px Switch Matrix Status Register123
- Nx Switch Matrix Status Register124
- Tx Switch Matrix Status Register125
Sequencer127
- Sequencer Features127
- Sequencer Overview127
- Sequencer Commands127
- Sequencer Operation128
- Sequencer and FIFO Registers130
AFE Interrupts136
- Interrupt Controller Interrupts136
- Configuring the Interrupts136
- Custom Interrupts136
- Interrupt Registers137
Sleep and Wake-Up Timer143
- Sleep and Wake-Up Timer Features143
- Sleep and Wake-Up Timer Overview143
- Configuring a Defined Sequence Order143
- Recommended Sleep and Wake-Up Timer Operation143
- Sleep and Wake-Up Timer Registers144
Use Case Configurations148
- Hibernate Mode While Maintaining a DC Bias to the Sensor148
- Measuring a DC Current Output149
- Pulse Test (Chronoamperometry)151
- Cyclic Voltammetry152
- AC Impedance Measurement While Maintaining DC Bias to the Sensor154
DMA Controller160
- DMA Features160
- DMA Overview160
- DMA Analog die160
- DMA Architectural Concepts160
- DMA Operating Modes161
- Channel Control Data Structure161
- Source Data End Pointer162
- Destination Data End Pointer162
- Control Data Configuration162
- DMA Priority164
- DMA Transfer Types164
- DMA Interrupts and Exceptions167
- Endian Operation169
- DMA Channel Enable and Disable169
- DMA Initiator Enable169
- Power-Down Considerations169
Register Summary: DMA170
Register Details: DMA171
- Status Register171
- Configuration Register171
- Channel Primary Control Data Base Pointer Register171
- Channel Alternate Control Data Base Pointer Register171
- Channel Software Request Register171
- Channel Request Mask Set Register172
- Channel Request Mask Clear Register172
- Channel Enable Set Register172
- Channel Enable Clear Register173
- Channel Primary Alternate Set Register173
- Channel Primary Alternate Clear Register173
- Channel Priority Set Register173
- Channel Priority Clear Register174
- Bus Error Clear Register174
- Per Channel Bus Error Register174
- Per Channel Invalid Descriptor Clear Register176
- Channel Bytes Swap Enable Set Register176
- Channel Bytes Swap Enable Clear Register176
- Channel Source Address Decrement Enable Set Register176
- Channel Source Address Decrement Enable Clear Register177
- Channel Destination Address Decrement Enable Set Register177
- Channel Destination Address Decrement Enable Clear Register177
- FIFO Configuration Register178
- Data FIFO Read Register178
Flash Controller179
- Flash Controller Features179
- Flash Controller Overview179
- Supported Commands179
- Protection and Integrity Features179
- Flash Controller Operation179
- Flash Memory Structure180
- Flash Access181
- Reading Flash181
- Erasing Flash182
- Writing Flash182
- Keyhole Writes182
- Burst Writes182
- DMA Writes183
- Protection and Integrity183
- Key Register185
- Clock and Timings187
- Flash Operating Modes187
Register Summary: Flash Cache Controller189
Register Details: Flash Cache Controller (FLCC)190
- Status Register190
- Interrupt Enable Register192
- Command Register192
- Write Address Register193
- Write Lower Data Register193
- Write Upper Data Register195
- Lower Page Address Register195
- Upper Page Address Register195
- Key Register195
- Write Abort Address Register196
- Write Protection Register196
- Signature Register196
- User Configuration Register197
- IRQ Abort Enable (Lower Bits) Register197
- IRQ Abort Enable (Upper Bits) Register197
- ECC Configuration Register197
- ECC Status (Address) Register199
- Analog Devices Flash Security Register199
Sram200
- SRAM Features200
- Instruction Vs. Data SRAM200
- SRAM Retention in Hibernate Mode201
- SRAM Initialization201
Cache202
- Initialization in Cache and Instruction SRAM202
- Programming Guidelines202
Register Summary: Cache (FLCC)203
Register Details: Cache (FLCC)204
- Cache Status Register204
- Cache Setup Register204
- Cache Key Register204
Silicon Identification205
Register Summary: System (Digital Die)206
Register Details: System (Digital Die)207
- Analog Devices Identification (Digital Die) Register207
- Chip Identifier (Digital Die) Register207
- Serial Wire Debug Enable Register207
- Analog Devices Identification (Analog Die) Register207
- Chip Identification (Analog Die) Register207
- 16-Bit Scratch Register to Test Interdie Communications Register208
Digital Inputs and Outputs209
- Digital Inputs and Outputs Features209
- Digital Inputs and Outputs Overview209
- Digital Inputs and Outputs Operation209
- Interrupts210
- Digital die Port Mux211
- AFE die Digital Port Mux211
Register Summary: Digital Inputs and Outputs212
Register Details: Digital Inputs and Outputs214
- GPIO Port Configuration Registers214
- GPIO Port Output Enable Registers214
- GPIO Port Input/Output Pull-Up Enable Registers214
- GPIO Port Input Path Enable Registers215
- GPIO Port Registered Data Input Registers215
- GPIO Port Data Output Registers215
- GPIO Port Data Output Set Registers215
- GPIO Port Data Output Clear Registers217
- GPIO Port Pin Toggle Registers217
- GPIO Port Interrupt Polarity Registers217
- GPIO Port Interrupt a Enable Registers217
- GPIO Port Interrupt B Enable Registers218
- GPIO Port Interrupt Status Registers218
- GPIO Port Drive Strength Select Registers218
- AFE GPIO Port Configuration Register218
- AFE GPIO Port Output Enable Register219
- AFE GPIO Port Output Pull-Up and Pull-Down Enable Register219
- AFE GPIO Port Input Path Enable Register219
- AFE GPIO Port Registered Data Input219
- AFE GPIO Port Data Output Register219
- AFE GPIO Port Data Output Set Register220
- AFE GPIO Port Data Output Clear Register220
- AFE GPIO Port Pin Toggle Register220
I 2 C Serial Interface221
- I 2 C Features221
- I 2 C Overview221
- I 2 C Operation221
- I 2 C Operating Modes223
Register Summary: I 2 C226
Register Details: I 2 C227
- Initiator Control Register227
- Initiator Status Register227
- Initiator Receive Data Register228
- Initiator Transmit Data Register228
- Initiator Receive Data Count Register229
- Initiator Current Receive Data Count Register229
- First Initiator Address Byte Register229
- Second Initiator Address Byte Register229
- Serial Clock Period Divisor Register230
- Target Control Register230
- Target I 2 C Status, Error, and IRQ Register231
- Target Receive Register232
- Target Transmit Register232
- Hardware General Call ID Register232
- First Target Address Device ID Register232
- Second Target Address Device ID Register234
- Third Target Address Device ID Register234
- Fourth Target Address Device ID Register234
- Initiator and Target FIFO Status Register234
- Initiator and Target Shared Control Register235
- Automatic Stretch Control for Initiator and Target Mode Register235
Serial Peripheral Interfaces237
- SPI Features237
- SPI Overview237
- SPI Operation237
- SPI Transfer Initiation238
- SPI Interrupts240
- SPI Wire-Or'ed Mode240
- SPI CSERR Condition241
- Spi Dma241
- SPI and Power-Down Modes242
Register Summary: SPI0/SPI1243
Register Details: SPI0/SPI1244
- Status Registers244
- Receive Registers245
- Transmit Registers245
- Baud Rate Selection Registers245
- Configuration Registers245
- Interrupt Configuration Registers247
- Transfer Byte Count Registers248
- DMA Enable Registers248
- FIFO Status Registers249
- Read Control Registers249
- Flow Control Registers250
- Wait Timer for Flow Control Registers252
- Chip Select Override Registers252
UART Serial Interface253
- UART Overview253
- UART Features253
- UART Operation253
Register Summary: UART256
Register Details: UART257
- Transmit Holding Register257
- Receive Buffer Register257
- Interrupt Enable Register257
- Interrupt Identification Register258
- Line Control Register258
- Modem Control Register259
- Line Status Register259
- Modem Status Register260
- Scratch Buffer Register260
- FIFO Control Register260
- Fractional Baud Rate Register261
- Baud Rate Divider Register261
- Second Line Control Register261
- UART Control Register262
- Receive FIFO Count Register262
- Transmit FIFO Count Register262
- RS485 Half-Duplex Control Register262
- Autobaud Control Register263
- Autobaud Status (Low) Register263
- Autobaud Status (High) Register263
Digital die General-Purpose Timers264
- Digital die General-Purpose Timers Features264
- General-Purpose Timers Overview264
- General-Purpose Timer Operations264
Register Summary: General-Purpose Timers267
Register Details: General-Purpose Timers268
- 16-Bit Synchronous Load Value Registers268
- 16-Bit Timer Synchronous Value Registers268
- Control Registers268
- Clear Interrupt Registers269
- Capture Registers269
- 16-Bit Asynchronous Load Value Registers270
- 16-Bit Timer Asynchronous Value Registers270
- Status Registers270
Analog die General-Purpose Timers272
- Analog die General-Purpose Timers Features272
- Afe Pwm272
Register Summary: Analog die General-Purpose Timers273
Register Details: Analog die General-Purpose Timers274
- 16-Bit Load Value Register274
- 16-Bit Timer Value Register274
- Control Register274
- Clear Interrupt Register275
- 16-Bit Load Value, Asynchronous Register275
- 16-Bit Timer Value, Asynchronous Register275
- Status Register275
- PWM Control Register276
- PWM Match Value Register276
- Interrupt Enable Register276
- 16-Bit Load Value Register277
- 16-Bit Timer Value Register277
- Control Register277
- Clear Interrupt Register278
- 16-Bit Load Value, Asynchronous Register278
- 16-Bit Timer Value, Asynchronous Register278
- Status Register279
- PWM Control Register279
- PWM Match Value Register279
AFE Watchdog Timer281
- Watchdog Timer Features and Block Diagram281
- Watchdog Timer Operation281
- Windowed Watchdog Feature281
- Interrupt Mode282
Register Summary: AFE Watchdog Timer283
Register Details: AFE Watchdog Timer284
- Watchdog Timer Load Value Register284
- Current Count Value Register284
- Watchdog Timer Control Register284
- Refresh Watchdog Register285
- Timer Status Register285
- Minimum Load Value Register286
Digital die Wake-Up Timer287
- Overview287
- Features287
- Regular and Periodic Modulo 60 Interrupts287
- Timer Matching Alarm Value Interrupts287
- WUT Functional Description287
- WUT Operating Modes288
- WUT Recommendations: Clock and Power288
Register Summary: Digital die Wake-Up Timer289
Register Details: Digital die Wake-Up Timer290
- Control 0 Register290
- Status 0 Register291
- Status 1 Register293
- Count 0 Register294
- Count 1 Register294
- Alarm 0 Register294
- Alarm 1 Register295
- Gateway Register295
- Control 1 Register295
- Status 2 Register296
- Snapshot 0 Register298
- Snapshot 1 Register298
- Snapshot 2 Register298
- Modulo Register299
- Count 2 Register299
- Alarm 2 Register301
- Status 6 Register301
Cyclic Redundancy Check303
- CRC Features303
- CRC Functional Description303
- CRC Data Transfer306
- CRC Interrupts and Exceptions306
- CRC Programming Model306
Register Summary: CRC308
Register Details: CRC309
- CRC Control Register309
- Input Data Word Register309
- CRC Result Register309
- Programmable CRC Polynomial Register309
- Input Data Bits Register309
- Input Data Byte Register310
Hardware Design Considerations311
- Typical System Configuration311
- Serial Wire Debug Interface311
- Rev. a | 6 of312

Brand	Analog Devices
Model	ADuCM356
Category	Microcontrollers
Language	English

Analog Devices ADuCM356 User Manual

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Analog Devices ADuCM356 Specifications