Reference Manual ADuCM356
TABLE OF CONTENTS
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Sleep and Wake-Up Timer Registers............. 144
Use Case Configurations...................................148
Hibernate Mode While Maintaining a DC
Bias to the Sensor........................................148
Measuring a DC Current Output.....................149
Pulse Test (Chronoamperometry).................. 151
Cyclic Voltammetry.........................................152
AC Impedance Measurement While
Maintaining DC Bias to the Sensor.............. 154
DMA Controller.................................................. 160
DMA Features................................................ 160
DMA Overview............................................... 160
DMA Analog Die.............................................160
DMA Architectural Concepts.......................... 160
DMA Operating Modes...................................161
Channel Control Data Structure..................... 161
Source Data End Pointer................................162
Destination Data End Pointer.........................162
Control Data Configuration.............................162
DMA Priority................................................... 164
DMA Transfer Types ..................................... 164
DMA Interrupts and Exceptions......................167
Endian Operation .......................................... 169
DMA Channel Enable and Disable ................169
DMA Initiator Enable...................................... 169
Power-Down Considerations..........................169
Register Summary: DMA...................................170
Register Details: DMA....................................... 171
Status Register...............................................171
Configuration Register....................................171
Channel Primary Control Data Base Pointer
Register........................................................171
Channel Alternate Control Data Base
Pointer Register............................................171
Channel Software Request Register..............171
Channel Request Mask Set Register............. 172
Channel Request Mask Clear Register..........172
Channel Enable Set Register.........................172
Channel Enable Clear Register......................173
Channel Primary Alternate Set Register........ 173
Channel Primary Alternate Clear Register..... 173
Channel Priority Set Register.........................173
Channel Priority Clear Register......................174
Bus Error Clear Register................................ 174
Per Channel Bus Error Register.....................174
Per Channel Invalid Descriptor Clear
Register........................................................176
Channel Bytes Swap Enable Set Register.....176
Channel Bytes Swap Enable Clear Register..176
Channel Source Address Decrement
Enable Set Register..................................... 176
Channel Source Address Decrement
Enable Clear Register.................................. 177
Channel Destination Address Decrement
Enable Set Register..................................... 177
Channel Destination Address Decrement
Enable Clear Register.................................. 177
FIFO Configuration Register.......................... 178
Data FIFO Read Register...............................178
Flash Controller ................................................ 179
Flash Controller Features...............................179
Flash Controller Overview..............................179
Supported Commands................................... 179
Protection and Integrity Features................... 179
Flash Controller Operation............................. 179
Flash Memory Structure.................................180
Flash Access..................................................181
Reading Flash................................................ 181
Erasing Flash................................................. 182
Writing Flash.................................................. 182
Keyhole Writes............................................... 182
Burst Writes....................................................182
DMA Writes.................................................... 183
Protection and Integrity.................................. 183
Key Register...................................................185
Clock and Timings..........................................187
Flash Operating Modes..................................187
Register Summary: Flash Cache Controller...... 189
Register Details: Flash Cache Controller
(FLCC).............................................................190
Status Register...............................................190
Interrupt Enable Register............................... 192
Command Register........................................ 192
Write Address Register.................................. 193
Write Lower Data Register............................. 193
Write Upper Data Register............................. 195
Lower Page Address Register........................195
Upper Page Address Register........................195
Key Register...................................................195
Write Abort Address Register.........................196
Write Protection Register............................... 196
Signature Register..........................................196
User Configuration Register...........................197
IRQ Abort Enable (Lower Bits) Register.........197
IRQ Abort Enable (Upper Bits) Register.........197
ECC Configuration Register...........................197
ECC Status (Address) Register......................199
Analog Devices Flash Security Register........ 199
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