Platform Descriptions
3-20 Issue 8.0 July 2002
Circuit pack keying prevents circuit packs from being accidentally inserted in
incorrect slots.
For detailed circuit pack descriptions and software compatibility information, refer
to Section 7, "Circuit Pack Descriptions."
High-Speed Shelf Interfaces 3
Front access cabling is provided through the interconnection panel (Figure 3-11).
Figure 3-11. Interconnection Panel (High-Speed Shelf)
The interconnection panel provides the following interfaces:
â– LINE GROWTH CHAN LINE (X) and LINE (Y): These connectors provide
an interface that allows access to the line growth channel (Z1 and Z2
bytes) of the OC-48 high-speed lines. These connectors are reserved for
use in a future release.
â– SECTION USER CHAN LINE (X) and LINE (Y): These connectors
provide an interface that allows access to the section user channel
(F1 byte) of the service and protection OC-48 high-speed lines. These
connectors are reserved for use in a future release.
SECTION OW
J45A
J61A
LINE OW
(EXP OW)
LINE
NO. X = 1W
LINE
NO. Y = 1E
LINE(X)
LINE(Y) LINE(Y)
J43A
NATL USE
J59A
J46A
J62A
INTRAOFFICE
LAN
PWR
-48A
-48B
-48A RTN
-48B RTN
LINE(X)
LINE(Y)
LINE(X)
LINE(Y)
(LOC OW)
J58A
J44A
SECTION
USER CHAN
J60A
J42AJ41A
J57A
LINE GROWTH
CHAN
LINE(X) LINE(X)
LINE(Y)
LINE(X)
LINE(Y)
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