Circuit Pack Descriptions
7-46 Issue 8.0 July 2002
In the transmit direction, the STS1E circuit pack accepts up to three 51.84 Mb/s
bipolar 3-zero substitution (B3ZS) coded EC-1 signals. These EC-1 signals are
split by the input protection interface. The outputs of the input protection interface
are connected to the line receiver and the Low Speed Switch (LSSW IN) circuit
pack (for protection). The line receiver recovers timing from the B3ZS-coded EC-1
signals and sends the EC-1 signals (as STS-1 signals) with the recovered clock to
the transmit/receive byte processor. The transmit/receive byte processor performs
B3ZS decoding, framing, descrambling, and overhead byte processing on the
received STS-1 signals. The transmit/receive byte processor then sends the clock
and STS-1 signals to the transmit pointer processor. The transmit pointer
processor performs frequency adjustment and frame alignment on the clock and
STS-1 signals using the 51.84 MHz system clock. The system clock is obtained
by locally dividing the 155.52 MHz clock signal from the TG3 (DS1) circuit pack by
three. The pointer processor sends the clock and STS-1 signals to the byte
processor. The byte processor scrambles and multiplexes the three STS-1 signals
into one 155 Mb/s signal. The high speed interface sends the 155.52 Mb/s signal
to the OC48 TRMTR circuit packs.
Receive Direction. 7In the receive direction, the high speed interface accepts the
155.52 Mb/s signal from the OC48 Receiver (OC48 RCVR) circuit pack. The high
speed interface recovers the 155.52 MHz clock signal, retimes the 155.52 Mb/s
signal, and sends it to the byte processor. The byte processor descrambles and
demultiplexes the 155.52 Mb/s signal into three 51.84 Mb/s STS-1 signals. The
three STS-1 signals are then sent to the receive pointer processor. The receive
pointer processor performs pointer processing on the three STS-1 signals and
sends a clock and three STS-1 signals that are synchronized to the system clock
to the transmit/receive byte processor. The transmit/receive byte processor
performs scrambling, B3ZS encoding, and overhead byte processing. The
transmit/receive byte processor then sends the clock and STS-1 signals to the line
driver. The line driver converts the STS-1 signals to three standard bipolar EC-1
output signals. The line driver sends the three standard B3ZS-coded EC-1 signals
to the output protection interface. The output protection interface selects the
signals from the line driver or the Low Speed Switch (LSSW OUT) circuit pack (for
protection) and outputs them to the STSX-1 panel (or equivalent).
Control Circuitry 7
The board controller circuit controls all the circuit pack activities. The board
controller circuit interfaces with the LNCTL circuit pack using the board controller
local area network (BCLAN). The STS1E circuit pack reports the status of the
circuit pack and the incoming EC-1 and 155.52 Mb/s signals, as well as the circuit
pack inventory information (CLEI code, serial number, etc.). The LNCTL circuit
pack uses the status information for fault detection and isolation. The STS1E
circuit pack also responds to control signals from the LNCTL circuit pack.
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