Circuit Pack Descriptions
7-66 Issue 8.0 July 2002
Timing Circuitry 7
The IS3 (1.3 STD) circuit pack accepts one 155.52 MHz clock signal from each of
the two Timing Generator, Stratum 3 - DS1 [TG3 (DS1)] circuit packs (primary and
secondary). During normal operation, the timing interface circuitry selects the
clock signal that is used and automatically switches to the other clock signal if it
detects a loss of signal. The board controller can also override the automatic clock
selection mode and force either clock signal to be selected.
The selected clock signal (155.52 MHz) is connected to the IS-3 line STS-3 byte
processor and the low speed STS-3 byte processor. The STS-3 byte processors
provide divide-by-three circuits that generate a 51.84 MHz signal. The 51.84 MHz
signal from the divide-by-three circuit on the IS-3 line STS-3 byte processor is
distributed to the receive circuitry of the IS-3 line STS-3 byte processor and the
receive pointer processor. The 51.84 MHz signal from the divide-by-three circuit
on the low speed STS-3 byte processor is distributed to the transmit circuitry of
the low speed STS-3 byte processor and the transmit pointer processor.
Protection Circuitry 7
Low Speed Interface Protection. 7Optional 1+1 nonrevertive IS3 (1.3 STD) circuit
pack protection in the transmit (toward the OC-48 line) and/or receive (toward the
IS-3 line) direction is provided. For 1+1 nonrevertive protection, two IS3 (1.3 STD)
circuit packs must be placed in adjacent “A” and “B” low speed interface slots of
the Low Speed Shelf - System Controller (for example, LS INTFC slots 2A and
2B). Both IS3 (1.3 STD) circuit packs transmit the same IS-3 signal toward the
lightguide cross-connect panel (or equivalent). Both IS3 (1.3 STD) circuit packs
receive the same IS-3 signal from the lightguide cross-connect panel (or
equivalent) and transmit STS-3/3c signals to the OC48 TRMTR circuit pack. The
IS3 circuit packs continuously monitor the incoming active and standby IS-3
signals. If the active IS-3 signal fails, the LNCTL circuit pack broadcasts a switch
request to the board controller on the OC48 TRMTR circuit pack via the BCLAN.
In the transmit (toward the OC-48 line) direction only, the OC48 TRMTR circuit
pack selects the standby STS-3/3c signal from the standby IS3 (1.3 STD) circuit
pack. The IS-3 (1.3 STD) circuit pack also supports 1+1 nonrevertive protection of
the IS-3 data communications channels.
High Speed Protection . 7If an OC-48 signal fails or is degraded, the LNCTL circuit
pack broadcasts a switch request to the board controllers on the IS3 (1.3 STD)
circuit packs via the BCLAN. In the transmit direction, the IS3 (1.3 STD) circuit
packs perform head-end bridges. In the FT-2000 OC-48 Add/Drop-Rings
Terminal, the STS-3/3c signals (155.52 Mb/s) are provided to the OC48 TRMTR
A/D circuit packs for lines 1E and 1W. In the receive direction, the IS3 (1.3 STD)
circuit packs perform tail-end switches. In the FT-2000 OC-48 Add/Drop-Rings
Terminal, selector circuitry on the IS3 (1.3 STD) circuit packs accepts the
STS-3/3c signals from the OC48 RCVR A/D circuit pack opposite of the
configured direction.
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