Circuit Pack Descriptions
Issue 8.0 July 2002
7-67
Synchronization Reference Protection. 7Synchronization reference switching is
done by selecting the primary or secondary synchronization reference signal from
the TG3 (DS1) circuit packs. The timing interface circuitry of the IS3 (1.3 STD)
circuit pack monitors these synchronization reference signals and can
autonomously select the primary or secondary. The LNCTL circuit pack can inhibit
this autonomous selection and make its own selection.
Fault Detection Circuitry 7
Monitoring and Testing. 7The board controller circuit monitors all the activities on
the circuit pack. The IS3 (1.3 STD) circuit pack has an in-service and
out-of-service built-in test capability. In-service testing is continuous. If an error
occurs, the board controller reports the error to the LNCTL circuit pack using the
board controller local area network (BCLAN). An out-of-service test is performed
whenever the IS3 (1.3 STD) circuit pack is inserted in a slot or when a reset is
performed.
Loopbacks. 7The IS3 (1.3 STD) circuit pack provides IS-3 and STS-3/3c loopbacks
for fault isolation and remote testing. The IS-3 loopback loops the input from the
IS-3 line back to the output of the IS-3 line via a loop connection in the low speed
STS-3 byte processor. This loopback does not loop the IS-3 DCC overhead
channel. The STS-3/3c loopback loops the STS-3/3c signal from the OC-48 line
back to the STS-3/3c signal transmitted toward the OC-48 line via a loop
connection in the IS-3 line STS-3 byte processor. The IS-3 and STS-3/3c
loopback paths include the transmit and receive pointer processors.
These loopbacks are implemented in response to craft interface terminal (CIT)
commands (via the SYSCTL and LNCTL circuit packs) and controlled by the
board controller.
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