Circuit Pack Descriptions
Issue 8.0 July 2002
7-111
signal (LOS). Timing is also extracted and the data is regenerated. The STS-48
data signal and 2.5 GHz clock signal are then passed to the byte demultiplexer.
The byte demultiplexer receives the STS-48 data signal from the
optical-to-electrical converter and demultiplexes the STS-48 data signal to sixteen
155.52 Mb/s signals. The sixteen 155.52 Mb/s data signals and a 155.52 MHz
clock signal are sent to the receive byte processor in a parallel format.
The receive byte processor frames on the incoming signals and converts them to
16 byte serial 155.52 Mb/s data signals. The SONET section overhead bytes are
also extracted and sent to the optional Orderwire (OW) circuit pack. A
synchronization reference signal (155.52 MHz) is also generated and sent to the
phase-locked loop (PLL) circuit.
The sixteen 155.52 Mb/s signals are then passed to the transmit byte processor.
The transmit byte processor combines the pointer and payload information from
the 155.52 Mb/s signals to form a parallel format. The 155.52 Mb/s signals are
then passed to the byte multiplexer circuit.
The byte multiplexer circuit bit interleaves the 155.52 Mb/s signals into a single
2.488 Gb/s STS-48 serial data stream and passes it to the electrical-to-optical
module.
The electrical-to-optical module converts the STS-48 signal to an optical OC-48
signal. A single line distributed feedback laser with driver and control circuits,
converts the electrical signal to optical pulses for transmission.
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