Circuit Pack Descriptions
7-112 Issue 8.0 July 2002
Control Circuitry 7
The board controller circuit controls all the circuit pack activities. The board
controller circuit interfaces with the System Controller (SYSCTL) circuit pack via
the board controller local area network (BCLAN).
The OC48 REGENR circuit pack reports the status of the circuit pack and the
incoming OC-48 signal, as well as inventory information (CLEI code, serial
number, etc.). The status information is used by the SYSCTL circuit pack for fault
detection and isolation. Conversely, the OC48 REGENR circuit pack responds to
control signals from the SYSCTL circuit pack.
The board controller also interfaces with the receive byte processor and transmit
byte processor to access the F1 byte. The F1 byte is used for communication
between repeater sites and FT-2000 OC-48 Add/Drop-Rings Terminals (Release
4 and later).
Timing Circuitry 7
The receive byte processor of the OC48 REGENR circuit pack generates a
155.52 MHz reference signal from the 2.5 GHz clock signal and sends it to the
phase-locked loop (PLL) circuit. The PLL circuit uses this 155.52 MHz reference
signal or the alarm indication signal (AIS) clock as a timing reference. The PLL
circuit provides a 2.5 GHz line rate clock signal to the multiplexer circuitry. If a
loss of clock condition is detected, a local 155.52 MHz signal is sent to the PLL
circuit.
Fault Detection Circuitry 7
Monitoring and Test. 7The board controller circuit monitors all the activities on the
circuit pack. The OC48 REGENR circuit pack has an in-service and
out-of-service built-in test capability. An out-of-service test is performed whenever
the OC48 REGENR circuit pack resets or is commanded to reset by the SYSCTL
circuit pack through the BCLAN. In-service testing is continuous. The board
controller circuit reports errors when they occur to the SYSCTL circuit pack via the
BCLAN. When the OC48 REGENR is inserted in a slot or reset, an out-of-service
test is performed.
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