Circuit Pack Descriptions
Issue 8.0 July 2002
7-117
The board controller on the TG3 (DS1) circuit pack detects hardware and software
faults on the circuit pack. When a fault occurs, the board controller is reset and the
FAULT LED on the circuit pack is continuously lighted. If an incoming DS1
reference signal fails, the FAULT LED will flash on and off.
General Description of Operation 7
The TG3 (DS1) circuit pack supports the synchronization features of the FT-2000
OC-48 Lightwave System in the following modes:
â– Externally timed mode: In the externally timed mode (phase locked mode
in releases prior to Release 5), each TG3 (DS1) circuit pack accepts a DS1
reference from an external stratum 3 or better clock. These references
synchronize the local terminal, and any others that may loop time to it, with
other network equipment operating under the same primary clock source.
Within the TG3 (DS1) circuit pack, a highly stable digital phase-locked loop
(DPLL) circuit removes any transient impairments on the DS1 reference for
improved jitter performance.
The DS1 references are continuously monitored for error-free operation. If
the selected reference becomes corrupted, the TG3 (DS1) circuit pack will
select the protection reference without causing service degradations. If
both DS1 inputs are corrupted, the DPLL circuit holds the on-board
oscillator frequency at the last good reference sample while the references
are repaired (holdover mode).
The LAA18 TG3 (DS1) circuit pack will also provide an external DS1
synchronization output signal to the office building integrated timing supply
(BITS) clock or other SONET network elements in an office. This DS1
output signal is derived directly from the 25.92 MHz line reference signal.
â– Through timed mode: In the through timed mode (FT-2000 OC-48
Add/Drop-Rings Terminal only), the TG3 (DS1) circuit pack derives timing
from the incoming OC-48 high speed signals. The number 1 TG3 (DS1)
circuit pack accepts a 25.92 MHz line reference signal from the west OC48
RCVR circuit pack and derives the internal synchronization clock used by
the east OC48 TRMTR (for through traffic), DS3 circuit packs terminating
add/drop traffic from line 1E, and STS1E, OC3 (1.3 STD), or OC12 (1.3
STD) circuit packs terminating add/drop traffic from line 1W. The number 2
TG3 (DS1) circuit pack accepts a 25.92 MHz line reference signal from the
east OC48 RCVR circuit pack and derives the internal synchronization
clock used by the west OC48 TRMTR (for through traffic), DS3 circuit
packs terminating add/drop traffic from line 1W, and STS1E or OC3 (1.3
STD) circuit packs terminating add/drop traffic from line 1E. If the reference
signals are corrupted or lost (for example, because of a cable cut), the
DPLL circuit holds the on-board oscillator frequency at the last good
reference sample (holdover mode).
The TG3 (DS1) circuit pack also provides an external DS1 synchronization
output signal to the office BITS clock or other SONET network elements in
an office. The LAA18 TG3 (DS1) circuit pack derives the DS1 output signal
directly from the 25.92 MHz line reference signal.
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