Circuit Pack Descriptions
7-118 Issue 8.0 July 2002
■ Free running mode: In the free running mode, the TG3 (DS1) circuit pack
derives timing from a highly stable crystal oscillator. This oscillator has a
long-term accuracy better than ±4.6 ppm.
■ Line Timed: In line timed mode (FT-2000 ADR Terminal Release 7.1.0 and
later software), the TG3 (DS1) circuit pack derives timing from the
incoming OC-48 high-speed signal. The number 1 TG3 (DS1) circuit pack
accepts a 25.92 MHz line reference signal from the west OC48 RCVR
circuit pack and derives the internal synchronization clock used by the east
OC48 TRMTR. The number 2 TG3 (DS1) circuit pack accepts a 25.92 MHz
line reference signal from the east OC48 RCVR circuit pack and derives
the internal synchronization clock used by the west OC48 TRMTR. As a
provisioning option, the user may choose which OC-48 line to derive timing
from (e.g., E, W, or Auto). Also, as a provisioning option, the user may
choose the backup option (Backup-E, Backup-W, Auto, or none). The type
switching is always revertive.
Detailed Description of Operation 7
Control Circuitry 7
Figure 7-35 shows an overall block diagram of the LAA18 TG3 (DS1) circuit pack
[the LAA18 replaces the LAA17 TG3 (DS1), which was discontinued]. The board
controller circuit controls all the circuit pack activities. The board controller circuit
interfaces with the LNCTL circuit pack via the BCLAN.
The TG3 (DS1) circuit pack reports the status of the circuit pack and the timing
references, as well as inventory information (CLEI code, serial number, etc.). The
status information is used by the LNCTL circuit pack for fault detection and
isolation. Conversely, the TG3 (DS1) circuit pack responds to control signals from
the LNCTL circuit pack.
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