Reference Manual ADuCM356
CYCLIC REDUNDANCY CHECK
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Table 399. 8-Bit Polynomial Programming Register Format, MSB First Calculation (Continued)
Register Bit(s) Value
[7:0] 0x08B0
Initial Seed Programmed in CRC Result Register (Result) [31:24] CRC seed
[23:16] 0x08B0
[15:8] 0x08B0
[7:0] 0x08B0
8-Bit Polynomial Programming for LSB First
Calculation
Polynomial: CRC-8-ATM
x
8
+ x
2
+ x + 1 = 1000 0011 (1) = 0x83
where the smallest exponent (x
0
term) is implied. Therefore, the
polynomial is 1000 0011.
When right justified in the polynomial register, the register format is
detailed in Table 400.
Table 400. 8-Bit Polynomial Programming Register Format, LSB First Calculation
Register Bit(s) Value
CRC Polynomial Register (POLY) [31:24] 0x08B0
[23:16] 0x08B0
[15:8] 0x08B0
[7:0] 1000 0011
CRC Result Register (Result) [31:24] 0x08B0
[23:16] 0x08B0
[15:8] 0x08B0
[7:0] CRC result
Initial Seed Programmed in CRC Result Register (Result) [31:24] 0x08B0
[23:16] 0x08B0
[15:8] 0x08B0
[7:0] CRC seed
The CRC engine uses the following 32-bit CRC polynomial as the
default (as per the IEEE 802.3 standard):
g(x) = x
32
+ x
26
+ x
23
+ x
22
+ x
16
+ x
12
+ x
11
+ x
10
+ x
8
+ x
7
+ x
5
+ x
4
+ x
2
+ x + 1
This value is programmed for MSB first calculation by default as
shown in Table 401.
Table 401. Default CRC Polynomial Register (POLY) Value
Bit(s) Value
[31:24] 0x04
[23:16] 0xC1
[15:8] 0x1D
[7:0] 0xB7
Reset and Hibernate Modes
The CRC configuration bits are retained, except for the block ena-
ble bit (CTL, Bit 0). The block must be enabled again after exiting
hibernate mode. The CRC polynomial and CRC result registers are
retained after exiting hibernate mode. See Table 402 for details on
the CRC registers after a reset and in hibernate mode.
Table 402. Reset and Hibernate by Register
Register Reset Hibernate
CTL 0x10000000 Apart from EN, all other bits retained
POLY 0x04C11DB7 Retained
IPDATA 0x0 Not retained
Result 0x0 Retained
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