ARM CoreLink GIC-600AE

Arm
®
CoreLink™ GIC-600AE Generic Interrupt Controller
Technical Reference Manual
Document ID: 101206_0003_04_en
Issue: 04
Revisions
Change Location
Updated the Usage constraints. Added a note about which
combinations of BLK and SMID are not permitted.
5.10.8 FMU_SMEN, Safety Mechanism Enable register on
page 187
Updated the Usage constraints. Added a note about which
combinations of BLK and SMID are not permitted.
5.10.9 FMU_SMINJERR, Safety Mechanism Inject Error
register on page 188
Updated the description of Safety Mechanism ID 0, for
all blocks. Added extra content about handling an SMID:0
response.
6.2.5 Safety Mechanism IDs on page 199
Added the BLK and SMID field information. Added
information about FMU_STATUS.idle.
6.2.5.2 Injecting an error in a Safety Mechanism on page
202
Added extra content 6.2.6 Ping mechanisms on page 202
Added extra information and an example of a 64-bit write
access
6.2.7 Lock and key mechanism on page 205
Added new content Power management on page 208
Table C-5: Differences between issue 0002-03 and issue 0003-04
Change Location
Replaced the non-inclusive language for:
•
The type of ACE-Lite interface. The document now uses
manager and subordinate interfaces.
•
The type of AXI4-Stream interface and GIC Stream interface. The
document now uses transmitter and receiver interfaces.
Throughout the document
Corrected a signal name, that is, gits_transr_page_offset becomes
its_transr_page_offset
•
3.1.2 Distributor ACE-Lite subordinate
interface on page 27
•
4.12 MSI-64 on page 65
Corrected the maximum number of outstanding write acceptance
capabilities from 128 to 256
3.3.1 ITS ACE-Lite subordinate interface on
page 36
Added Figure 4-3: MSI-64 Encapsulator with DeviceID sent in the
data[63:32] bits on page 66
4.12 MSI-64 on page 65
Added more information about programming the GICP_IRQCR.SPIID
field
Overflow interrupt on page 68
Corrected the corrupted SGI number formula Table 4-10: SGI RAM errors, records 3-4 on
page 78
•
Corrected the Type assignment of GICD_CHIPSR from RW to
RO
•
Corrected the number of Reserved registers for GICD_NSACRn
when affinity routing is enabled
5.2 Distributor registers (GICD/GICDA)
summary on page 98
Corrected the description of the *_busy bits 5.2.6 GICD_CHIPSR, Chip Status Register on
page 107
Corrected the GICR_ICFGR1 reset value 5.5 Redistributor registers for SGIs and PPIs
summary on page 130
Added the Revision field value for r0p3 •
5.2.3 GICD_IIDR, Distributor Implementer
Identification Register on page 103
•
5.4.1 GICR_IIDR, Redistributor
Implementation Identification Register on
page 122
•
5.6.1 GITS_IIDR, ITS Implementer
Identification Register on page 138
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