Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 214
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
1 DQS1_N D_06 N 43 DQS-N
1DQ11 D_05 P 42 –
1DQ10 D_04 N 41 –
1DQ9 D_03 P 40 –
1DQ8 D_02 N 39 –
1DM1 D_01 P 38 –
1– D_00N 37 –
1DQ7 C_11 P 36 –
1DQ6 C_10 N 35 –
1DQ5 C_09 P 34 –
1DQ4 C_08 N 33 –
1 DQS0_P C_07 P 32 DQS-P
1 DQS0_N C_06 N 31 DQS-N
1DQ3 C_05 P 30 –
1DQ2 C_04 N 29 –
1 DQ1 C_03 P 28 CCIO-P
1 DQ0 C_02 N 27 CCIO-N
1 DM0 C_01 P 26 CCIO-P
1 RESET_N C_00 N 25 CCIO-N
1 RAS_N B_11 P 24 CCIO-P
1 CAS_N B_10 N 23 CCIO-N
1 WE_N B_09 P 22 CCIO-P
1BA2 B_08 N 21 CCIO-N
1CK_P B_07 P 20 DQS-P
1CK_N B_06 N 19 DQS-N
1BA1 B_05 P 18 –
1BA0 B_04 N 17 –
1CS_N B_03 P 16 –
1ODT B_02 N 15 –
1CKE B_01 P 14 –
1 A12 B_00 N 13 –
1 A11 A_11 P 12 –
1 A10 A_10 N 11 –
1A9 A_09 P 10 –
Table 1-69: 16-Bit DDR3 Interface Contained in One Bank (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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