Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 220
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
1 – A_00N 1 –
1VRN – SE 0 –
2VRP – SE 49 –
2– D_11P 48 –
2– D_10N 47 –
2– D_09P 46 –
2– D_08N 45 –
2– D_07P 44 DQS-P
2– D_06N 43DQS-N
2– D_05P 42 –
2– D_04N 41 –
2– D_03P 40 –
2– D_02N 39 –
2– D_01P 38 –
2– D_00N 37 –
2– C_11P 36 –
2– C_10N 35 –
2– C_09P 34 –
2– C_08N 33 –
2– C_07P 32 DQS-P
2– C_06N 31DQS-N
2– C_05P 30 –
2– C_04N 29 –
2 – C_03 P 28 CCIO-P
2 – C_02 N 27 CCIO-N
2 – C_01 P 26 CCIO-P
2 ODT C_00 N 25 CCIO-N
2 RAS_N B_11 P 24 CCIO-P
2 CAS_N B_10 N 23 CCIO-N
2 WE_N B_09 P 22 CCIO-P
2 BA2 B_08 N 21 CCIO-N
2CK_P B_07 P 20 DQS-P
2CK_N B_06 N 19 DQS-N
2BA1 B_05 P 18 –
Table 1-71: 64-Bit DDR3 Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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