Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 222
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
3DQ20 C_08 N 33 –
3 DQS2_P C_07 P 32 DQS-P
3 DQS2_N C_06 N 31 DQS-N
3DQ19 C_05 P 30 –
3DQ18 C_04 N 29 –
3 DQ17 C_03 P 28 CCIO-P
3 DQ16 C_02 N 27 CCIO-N
3 DM2 C_01 P 26 CCIO-P
3 – C_00 N 25 CCIO-N
3 DQ15 B_11 P 24 CCIO-P
3 DQ14 B_10 N 23 CCIO-N
3 DQ13 B_09 P 22 CCIO-P
3 DQ12 B_08 N 21 CCIO-N
3 DQS1_P B_07 P 20 DQS-P
3 DQS1_N B_06 N 19 DQS-N
3DQ11 B_05 P 18 –
3DQ10 B_04 N 17 –
3DQ9 B_03 P 16 –
3DQ8 B_02 N 15 –
3DM1 B_01 P 14 –
3– B_00N 13 –
3DQ7 A_11 P 12 –
3DQ6 A_10 N 11 –
3DQ5 A_09 P 10 –
3DQ4 A_08 N 9 –
3 DQS0_P A_07 P 8 DQS-P
3 DQS0_N A_06 N 7 DQS-N
3DQ3 A_05 P 6 –
3DQ2 A_04 N 5 –
3DQ1 A_03 P 4 –
3DQ0 A_02 N 3 –
3DM0 A_01 P 2 –
3RESET_N A_00 N 1 –
3VRN – SE 0 –
Table 1-71: 64-Bit DDR3 Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V