Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 223
UG586 November 30, 2016
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Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Table 1-72 shows an example of a 72-bit DDR3 interface contained within three banks. This
example is for a 4 Gb UDIMM using nine 4 Gb x8 components. The serial presence detect
(SPD) pins are not used here. CB[7:0] is represented as DQ[71:64] and S0# as CS_N for
consistency with the component design examples in Table 1-69, page 213, Table 1-70,
page 215, and Table 1-71, page 218.
Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
1VRP – SE 49 –
1DQ63 D_11 P 48 –
1DQ62 D_10 N 47 –
1DQ61 D_09 P 46 –
1DQ60 D_08 N 45 –
1 DQS7_P D_07 P 44 DQS-P
1 DQS7_N D_06 N 43 DQS-N
1DQ59 D_05 P 42 –
1DQ58 D_04 N 41 –
1DQ57 D_03 P 40 –
1DQ56 D_02 N 39 –
1DM7 D_01 P 38 –
1– D_00N 37 –
1DQ55 C_11 P 36 –
1DQ54 C_10 N 35 –
1DQ53 C_09 P 34 –
1DQ52 C_08 N 33 –
1 DQS6_P C_07 P 32 DQS-P
1 DQS6_N C_06 N 31 DQS-N
1DQ51 C_05 P 30 –
1DQ50 C_04 N 29 –
1DQ49 C_03 P 28 CCIO-P
1DQ48 C_02 N 27 CCIO-N
1 DM6 C_01 P 26 CCIO-P
1 – C_00 N 25 CCIO-N
1DQ47 B_11 P 24 CCIO-P
1DQ46 B_10 N 23 CCIO-N
1DQ45 B_09 P 22 CCIO-P
1DQ44 B_08 N 21 CCIO-N
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