Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 224
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
1 DQS5_P B_07 P 20 DQS-P
1 DQS5_N B_06 N 19 DQS-N
1DQ43 B_05 P 18 –
1DQ42 B_04 N 17 –
1DQ41 B_03 P 16 –
1DQ40 B_02 N 15 –
1DM5 B_01 P 14 –
1– B_00N 13 –
1DQ39 A_11 P 12 –
1DQ38 A_10 N 11 –
1DQ37 A_09 P 10 –
1DQ36 A_08 N 9 –
1 DQS4_P A_07 P 8 DQS-P
1 DQS4_N A_06 N 7 DQS-N
1DQ35 A_05 P 6 –
1DQ34 A_04 N 5 –
1DQ33 A_03 P 4 –
1DQ32 A_02 N 3 –
1DM4 A_01 P 2 –
1 A_00N 1 –
1VRN – SE 0 –
2VRP – SE 49 –
2DQ71 D_11 P 48 –
2DQ70 D_10 N 47 –
2DQ69 D_09 P 46 –
2DQ68 D_08 N 45 –
2 DQS8_P D_07 P 44 DQS-P
2 DQS8_N D_06 N 43 DQS-N
2DQ67 D_05 P 42 –
2DQ66 D_04 N 41 –
2DQ65 D_03 P 40 –
2DQ64 D_02 N 39 –
2DM8 D_01 P 38 –
2– D_00N 37 –
Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V