Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 225
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
2– C_11P 36 –
2– C_10N 35 –
2– C_09P 34 –
2– C_08N 33 –
2– C_07P 32 DQS-P
2– C_06N 31DQS-N
2– C_05P 30 –
2– C_04N 29 –
2 – C_03 P 28 CCIO-P
2ODT0 C_02 N 27 CCIO-N
2CKE0 C_01 P 26 CCIO-P
2 CS_N0 C_00 N 25 CCIO-N
2RAS_N B_11 P 24 CCIO-P
2CAS_N B_10 N 23 CCIO-N
2WE_N B_09 P 22 CCIO-P
2BA2 B_08 N 21 CCIO-N
2CK_P B_07 P 20 DQS-P
2CK_N B_06 N 19 DQS-N
2BA1 B_05 P 18 –
2BA0 B_04 N 17 –
2 A15 B_03 P 16 –
2 A14 B_02 N 15 –
2 A13 B_01 P 14 –
2 A12 B_00 N 13 –
2 A11 A_11 P 12 –
2 A10 A_10 N 11 –
2A9 A_09 P 10 –
2A8 A_08 N 9 –
2A7 A_07 P 8 DQS-P
2A6 A_06 N 7 DQS-N
2A5 A_05 P 6 –
2A4 A_04 N 5 –
2A3 A_03 P 4 –
2A2 A_02 N 3 –
Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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