Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 226
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
2A1 A_01 P 2 –
2A0 A_00 N 1 –
2VRN – SE 0 –
3VRP – SE 49 –
3DQ31 D_11 P 48 –
3DQ30 D_10 N 47 –
3DQ29 D_09 P 46 –
3DQ28 D_08 N 45 –
3 DQS3_P D_07 P 44 DQS-P
3 DQS3_N D_06 N 43 DQS-N
3DQ27 D_05 P 42 –
3DQ26 D_04 N 41 –
3DQ25 D_03 P 40 –
3DQ24 D_02 N 39 –
3DM3 D_01 P 38 –
3– D_00N 37 –
3DQ23 C_11 P 36 –
3DQ22 C_10 N 35 –
3DQ21 C_09 P 34 –
3DQ20 C_08 N 33 –
3 DQS2_P C_07 P 32 DQS-P
3 DQS2_N C_06 N 31 DQS-N
3DQ19 C_05 P 30 –
3DQ18 C_04 N 29 –
3DQ17 C_03 P 28 CCIO-P
3DQ16 C_02 N 27 CCIO-N
3 DM2 C_01 P 26 CCIO-P
3 – C_00 N 25 CCIO-N
3DQ15 B_11 P 24 CCIO-P
3DQ14 B_10 N 23 CCIO-N
3DQ13 B_09 P 22 CCIO-P
3DQ12 B_08 N 21 CCIO-N
3 DQS1_P B_07 P 20 DQS-P
3 DQS1_N B_06 N 19 DQS-N
Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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Xilinx Zynq-7000 Specifications

General

Series	Zynq-7000
Number of Cores	Dual-core
Processor Speed	Up to 1 GHz
Device Type	SoC
Logic Cells	Up to 350K
DSP Slices	Up to 900
External Memory Interfaces	DDR3, DDR2, LPDDR2
I/O Standards	LVCMOS, HSTL, SSTL
Operating Temperature	-40°C to +100°C (Industrial), 0°C to +85°C (Commercial)
Package Options	Various BGA packages
I/O Voltage	3.3V