Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 227
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
3DQ11 B_05 P 18 –
3DQ10 B_04 N 17 –
3DQ9 B_03 P 16 –
3DQ8 B_02 N 15 –
3DM1 B_01 P 14 –
3– B_00N 13 –
3DQ7 A_11 P 12 –
3DQ6 A_10 N 11 –
3DQ5 A_09 P 10 –
3DQ4 A_08 N 9 –
3 DQS0_P A_07 P 8 DQS-P
3 DQS0_N A_06 N 7 DQS-N
3DQ3 A_05 P 6 –
3DQ2 A_04 N 5 –
3DQ1 A_03 P 4 –
3DQ0 A_02 N 3 –
3DM0 A_01 P 2 –
3RESET_N A_00 N 1 –
3VRN – SE 0 –
Table 1-72: 72-Bit DDR3 UDIMM Interface in Three Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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