Xilinx Zynq-7000

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 218
UG586 November 30, 2016
www.xilinx.com
Chapter 1: DDR3 and DDR2 SDRAM Memory Interface Solution
Table 1-71 shows an example of a 64-bit DDR3 interface contained within three banks. This
example uses four 2 Gb x16 components.
2– B_00N 13 –
2DQ7 A_11 P 12 –
2DQ6 A_10 N 11 –
2DQ5 A_09 P 10 –
2DQ4 A_08 N 9 –
2 DQS0_P A_07 P 8 DQS-P
2 DQS0_N A_06 N 7 DQS-N
2DQ3 A_05 P 6 –
2DQ2 A_04 N 5 –
2DQ1 A_03 P 4 –
2DQ0 A_02 N 3 –
2DM0 A_01 P 2 –
2 RESET_N A_00 N 1 –
2VRN – SE 0 –
Table 1-71: 64-Bit DDR3 Interface in Three Banks
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
1VRP – SE 49 –
1DQ63 D_11 P 48 –
1DQ62 D_10 N 47 –
1DQ61 D_09 P 46 –
1DQ60 D_08 N 45 –
1 DQS7_P D_07 P 44 DQS-P
1 DQS7_N D_06 N 43 DQS-N
1DQ59 D_05 P 42 –
1DQ58 D_04 N 41 –
1DQ57 D_03 P 40 –
1DQ56 D_02 N 39 –
1DM7 D_01 P 38 –
1– D_00N 37 –
1DQ55 C_11 P 36 –
Table 1-70: 32-Bit DDR3 Interface Contained in Two Banks (Cont’d)
Bank Signal Name Byte Group I/O Type I/O Number
Special
Designation
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