Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 405
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
Design generation from MIG can be generated using the Create Design flow or the
Verify Pin Changes and Update Design flows. There is no difference between the flow
when generating the design from the MIG tool. Irrespective of the flow by which designs
are generated from the MIG tool, the XCI file is added to the Vivado tool project. The
implementation flow is the same for all scenarios because the flow depends on the XCI
file added to the project.
6. All MIG generated user design RTL and XDC files are automatically added to the project.
If files are modified and you wish to regenerate them, right-click the XCI file and select
Generate Output Products (Figure 3-29).
X-Ref Target - Figure 3-28
Figure 3-28: Vivado Tool Project Sources Window
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English