Xilinx Zynq-7000 User Manual

Zynq-7000 AP SoC and 7 Series FPGAs MIS v4.1 404
UG586 November 30, 2016
www.xilinx.com
Chapter 3: RLDRAM II and RLDRAM 3 Memory Interface Solutions
4. After generating the MIG design, the project window appears as shown in Figure 3-27.
5. After project creation, the XCI file is added to the Project Hierarchy. The same view also
displays the module hierarchies of the user design. The list of HDL and XDC files is
available in the IP Sources view in the Sources window. Double-clicking on any module
or file opens the file in the Vivado Editor. These files are read only.
X-Ref Target - Figure 3-27
Figure 3-27: Vivado Tool Project Window (After IP Generation)
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Xilinx Zynq-7000 Specifications

General

Brand	Xilinx
Model	Zynq-7000
Category	Motherboard
Language	English